CY7C1486V33(2004) データシートの表示（PDF） - Cypress Semiconductor
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CY7C1486V33 Datasheet PDF : 30 Pages
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PRELIMINARY
CY7C1480V33
CY7C1482V33
CY7C1486V33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
VDD
VDDQ
3.3V – 5%/+10% 2.5V – 5%
to VDD
Electrical Characteristics Over the Operating Range[12, 13]
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[12]
Input LOW Voltage[12]
Input Load Current
except ZZ and MODE
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
3.135
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
Input Current of MODE Input = VSS
–5
Input = VDD
Input Current of ZZ
Input = VSS
–30
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4.0-ns cycle, 250 MHz
Current
f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB1
Automatic CE
VDD = Max, Device Deselected, 4.0-ns cycle, 250 MHz
Power-down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB2
Automatic CE
VDD = Max, Device Deselected, All speeds
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CE
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5.0-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
ISB4
Automatic CE
VDD = Max, Device Deselected, All speeds
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
13. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD\
Max.
3.6
VDD
2.625
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
0.7
5
30
5
5
500
500
450
245
245
245
120
245
245
245
135
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Document #: 38-05283 Rev. *C
Page 19 of 30
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