CY7C1482V33-200BZXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C1482V33-200BZXC Datasheet PDF : 31 Pages
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CY7C1480V33
CY7C1482V33
CY7C1486V33
3.3V TAP AC Test Conditions
Input pulse levels ............................................... .VSS to 3.3V
Input rise and fall times ................................................... 1 ns
Input timing reference levels ...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
1.5V
2.5V TAP AC Test Conditions
Input pulse levels................................................. VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
2.5V TAP AC Output Load Equivalent
1.25V
TDO
ZO= 50Ω
50Ω
20pF
TDO
ZO= 50Ω
50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135 to 3.6V unless otherwise noted)[10]
Parameter
Description
Test Conditions
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –4.0 mA, VDDQ = 3.3V
IOH = –1.0 mA, VDDQ = 2.5V
IOH = –100 µA
VDDQ = 3.3V
VDDQ = 2.5V
IOL = 8.0 mA
VDDQ = 3.3V
IOL = 1.0 mA
VDDQ = 2.5V
IOL = 100 µA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND < VIN < VDDQ
Min.
2.4
2.0
2.9
2.1
2.0
1.7
–0.3
–0.3
–5
Max.
Unit
V
V
V
V
0.4
V
0.4
V
0.2
V
0.2
V
VDD + 0.3
V
VDD + 0.3
V
0.8
V
0.7
V
5
µA
Identification Register Definitions
Instruction Field
CY7C1480V33 CY7C1482V33 CY7C1486V33
(2M x36)
(4M x 18)
(1M x72)
Description
Revision Number (31:29)
000
000
000
Describes the version number
Device Depth (28:24)
01011
01011
01011 Reserved for internal use
Architecture/Memory Type(23:18) 000000
000000
000000 Defines memory type and architecture
Bus Width/Density(17:12)
100100
010100
110100 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 Allows unique identification of SRAM
vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID register
Notes:
10. All voltages referenced to VSS (GND).
11. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05283 Rev. *G
Page 15 of 31
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