K9F4G08U0M データシートの表示（PDF） - Samsung
部品番号
コンポーネント説明
メーカー
K9F4G08U0M Datasheet PDF : 41 Pages
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K9K8G08U1M
K9F4G08U0M
Advance
FLASH MEMORY
VALID BLOCK
Parameter
K9F4G08U0M
K9K8G08U1M
Symbol
NVB
NVB
Min
4,016
8,032*
Typ.
-
-
Max
4,096
8,192*
Unit
Blocks
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
* : Each K9F4G08U0M chip in the K9K8G08U1M has Maximun 80 invalid block.
AC TEST CONDITION
(K9F4G08U0M-XCB0 :TA=0 to 70°C, K9F4G08U0M-XIB0:TA=-40 to 85°C
K9F4G08U0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
K9F4G08U0M
0V to Vcc
5ns
Vcc/2
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Condition
Min
CI/O
VIL=0V
-
CIN
VIN=0V
-
Max
10
10
Unit
pF
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
WE
RE
H
L
L
H
L
H
L
H
H
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X(1)
X
X
X
X
X
H
X
X
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
WP
X
X
H
H
H
X
X
H
H
L
0V/VCC(2)
Mode
Command Input
Read Mode
Address Input(5clock)
Command Input
Write Mode
Address Input(5clock)
Data Input
Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
10
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