MB87L2250 データシートの表示（PDF） - Fujitsu

部品番号

コンポーネント説明

メーカー

MB87L2250

MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU

Fujitsu 

Product Profile

October 1998

Edition 1.1

MB87L2250 - MPEG2 Decoder

2.9. Audio Output

• Over sampling clock: 384 fs/256 fs

• Bit clock: 32 fs / 48 fs / 64 fs

• Support of different audio-DAC’s via serial I/F

• Fractional counter for audio clock generation

• Programmable bit order (MSB or LSB First)

• skip / repeat sample programmable

2.10. External RAM

• 16 Mbit SDRAM, 16 Bit data bus

• Pipelined Type, >83 MHz @ 81 MHz system clock

• Organisation: 2 banks, 2048 rows x 256 words

2.11. Synchronisation

• dedicated system synchronisation hardware for

- clock recovery (PCR handling)

- video / audio synchronisation (PTS / DTS handling)

- PWM generator for external VCXO control

• automatic hardware control (software control optional) for

- video output

- video decoder

- audio decoder

- PWM signal for 27 MHz VCXO

2.12. IC Card Interface

• two IC card interfaces with timer function

2.13. IIC Interface

• The I2C master interface supports I2C master mode with four operating modes:

- random access write, writing of one data byte to a specified address

- random access read, reading of one data byte from a specified address

- direct write, writing of a data burst

- direct read, reading of a data burst

2.14. General Purpose I/O

• 16 general purpose I/O‘s

• write data

- open drain output (programmable)

• read data

• IRQ sensitive (programmable)

- level / edge sensitive

2.15. Infra Red Receiver

Fujitsu Mikroelektronik GmbH Proprietary Information

5

Confidential

Share Link: