ARM9TDMI データシートの表示（PDF） - Unspecified

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ARM9TDMI

ARM9TDMI Processor Core

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List of Figures

ARM9TDMI Technical Reference Manual

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ARM DDI 0180A

Key to timing diagram conventions ............................................................................ xiii

ARM9TDMI processor block diagram ....................................................................... 1-3

ARM9TDMI processor core instruction pipeline ........................................................ 2-4

ARM9TDMI clock stalling using nWAIT ..................................................................... 3-4

Instruction fetch timing .............................................................................................. 3-6

Data access timings ................................................................................................ 3-10

ARM9TDMI reset behavior ...................................................................................... 3-14

ARM9TDMI LDC / STC cycle timing ......................................................................... 4-4

ARM9TDMI coprocessor clocking ............................................................................. 4-5

ARM9TDMI MCR / MRC transfer timing ................................................................... 4-9

ARM9TDMI interlocked MCR .................................................................................. 4-12

ARM9TDMI late cancelled CDP .............................................................................. 4-14

ARM9TDMI privileged instructions .......................................................................... 4-15

ARM9TDMI busy waiting and interrupts .................................................................. 4-18

ARM9TDMI coprocessor 15 MCRs ......................................................................... 4-19

Typical debug system ............................................................................................... 5-3

Breakpoint timing ...................................................................................................... 5-6

Watchpoint entry with data processing instruction .................................................... 5-8

Watchpoint entry with branch .................................................................................... 5-9

Test access port (TAP) controller state transitions .................................................. 5-12

Clock switching on entry to debug state .................................................................. 5-25

Debug exit sequence .............................................................................................. 5-31

Debug state entry .................................................................................................... 5-32

Copyright © 2000 ARM Limited. All rights reserved.

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