MT28S4M16LCTG-10 データシートの表示（PDF） - Micron Technology

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MT28S4M16LCTG-10

SYNCFLASH® MEMORY

Micron Technology 

COMMANDS

Truth Table 1 provides a quick reference of avail-

able commands for SDRAM-compatible operation. This

is followed by a written description of each command.

Additional truth tables appear later.

4 MEG x 16

SYNCFLASH MEMORY

TRUTH TABLE 1

SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION

(Notes: 1)

NAME (FUNCTION)

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

READ (Select bank, column and start READ burst)

WRITE (Select bank, column and start WRITE)

BURST TERMINATE

ACTIVE TERMINATE

LOAD COMMAND REGISTER

LOAD MODE REGISTER

Write Enable/Output Enable

Write Inhibit/Output High-Z

CS#

H

L

L

L

L

L

L

L

L

–

–

RAS# CAS# WE# DQM ADDR DQs NOTES

X

X

XX

X

X

H

H

HX

X

X

L

H

H X Bank/Row X

2

H

L

H X Bank/Col X

3

H

L

L X Bank/Col Valid 3, 4

H

H

LX

X

Active

L

H

LX

X

X

5

L

L

H X ComCode X

6, 7

L

L

L X OpCode X

8

–

–

–L

–

Active 9

–

–

–H

–

High-Z 9

NOTE:

1. CKE is HIGH for all commands shown.

2. A0–A11 provide row address, and BA0 and BA1 determine which bank is made active.

3. A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to.

4. A program setup command sequence (see Truth Table 2) must be completed prior to executing a WRITE.

5. ACTIVE TERMINATE is functionally equivalent to the SDRAM PRECHARGE command, however PRECHARGE (deactivate row

in bank or banks) is not required for SyncFlash memory. A10 LOW: BA0 and BA1 determine the bank being active

terminated. A10 HIGH: All banks active terminated and BA0 and BA1 are “Don’t Care.”

6. A0–A7 define the ComCode, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2.

7. LOAD COMMAND REGISTER (LCR) replaces the SDRAM AUTO REFRESH or SELF REFRESH command, which is not required

for SyncFlash memory. LCR is the first cycle for Flash memory command sequences. See Truth Table 2.

8. A0–A11 define the OpCode written to the mode register. The mode register can be dynamically loaded each cycle,

provided tMRD is satisfied. The contents of the nvmode register are automatically loaded into the mode register during

device initialization.

9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

4 Meg x 16 SyncFlash

MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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