MT28S4M16LCTG-10 データシートの表示（PDF） - Micron Technology

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MT28S4M16LCTG-10

SYNCFLASH® MEMORY

Micron Technology 

4 MEG x 16

SYNCFLASH MEMORY

PIN DESCRIPTIONS

54-PIN TSOP

NUMBERS

38

37

19

18, 17, 16

15, 39

23-26, 29-34,

22, 35

40

SYMBOL TYPE

CLK

Input

CKE

Input

CS#

Input

RAS#,

CAS#,

WE#

DQML,

DQMH

Input

Input

A0–A11 Input

RP#

Input

DESCRIPTION

Clock: CLK is driven by the system clock. All SyncFlash memory input

signals are sampled on the positive edge of CLK. CLK also increments

the internal burst counter and controls the output registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK

signal. Deactivating the clock provides STANDBY operation or CLOCK

SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down modes, where CKE

becomes asynchronous until after exiting the same mode. The input

buffers, including CLK, are disabled during power-down modes,

providing low standby power. CKE may be tied HIGH in systems where

power-down modes (other than RP# deep power-down) are not

required.

Chip Select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is

registered HIGH. CS# provides for external bank selection on systems

with multiple banks. CS# is considered part of the command code.

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

command being entered.

Input/Output Mask: DQM is an input mask signal for write accesses

and an output enable signal for read accesses. Input data is masked

when DQM is sampled HIGH during a WRITE cycle. The output buffers

are placed in a High-Z state (after a two-clock latency) when DQM is

sampled HIGH during a READ cycle. DQML corresponds to DQ0–DQ7

and DQMH corresponds to DQ8–DQ15. DQML and DQMH are

considered same state when referenced as DQM.

Address Inputs: A0–A11 are sampled during the ACTIVE command

(row-address A0–A11) and READ/WRITE command (column-address

A0–A7) to select one location in the respective bank. The address

inputs provide the Op-Code during LOAD MODE REGISTER command

and the operation code during a LOAD COMMAND REGISTER

command.

Initialize/Power-Down: Upon initial device power-up, a 100µs delay

after RP# has transitioned from LOW to HIGH is required for internal

device initialization, prior to issuing an executable command. RP#

clears the status register, sets the internal state machine (ISM) to the

array read mode, and places the device in the deep power-down

mode when LOW. All inputs, including CS#, are “Don’t Care” and all

outputs are High-Z. When RP# = VHH, all protection modes are ignored

during PROGRAM and ERASE. Also allows the device protect bit to be

set to “1” (protected) and allows the block protect bits at locations 0

and 15 to be set to “0” (unprotected) when brought to VHH. RP# must

be held HIGH during all other modes of operation.

(continued on next page)

4 Meg x 16 SyncFlash

MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01

5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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