GM6535 データシートの表示（PDF） - Hynix Semiconductor

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GM6535

60 MHz Universal Programmable Dual PLL Frequency synthesizer

Hynix Semiconductor 

D in

16-BIT Tx COUNTER

DIVIDE RATIO

16-BIT Rx COUNTER

DIVIDE RATIO

CLK

Last

Clock

ENB

NOTE: ENB must be low during the serial transfer.

Figure 13. Programming Format for Transmit and Receive Counters

(3-Pin Interfacing Scheme)

Control Register

Identifier = 1

D in

1

0

MSB

AUX DATA SELECT = 1

Control Register Data

TEST

BIT

AUX

Data

Select

REF

OUT

÷3/÷4

TxPD

Enable

RxPD

Enable

Ref PD

Enable

LSB

CLK

ENB

NOTE: ENB must be high during the serial transfer.

Figure 14. Programming Format for control Register

(4-Pin Interfacing Scheme)

AD in

D in

CLK

16-BIT Tx COUNTER

DIVIDE RATIO

16-BIT Rx COUNTER

DIVIDE RATIO

Last

Clock

ENB

NOTE: ENB must be low during the serial transfer.

Figure 15. Programming Format for Transmit and Receive Counters

(4-Pin Interfacing Scheme)

10

GM6535

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