GM6535 データシートの表示（PDF） - Hynix Semiconductor

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GM6535

60 MHz Universal Programmable Dual PLL Frequency synthesizer

Hynix Semiconductor 

GM6535

PIN DESCRIPTIONS

OSCin/OSCout

Reference Oscillator Input/Output (Pins8, 7)

These pins form a reference oscillator when

connected to an external parallel-resonant crystal

frequencies and reference frequencies for cordless

phone applications in various countries. OSCin may

also serve as input for an externally generated

reference signal which is typically ac coupled.

ADin, Din, CLK, ENB

Auxiliary Data In, Data In, Clock, Enable (Pins2, 3,

1, 4)

These four pins provide an MCU serial interface for

programming the reference counter, the transmit-

channel counter, and the receive-channel counter. They

also provide various controls of the PLL including the

power saving mode and the programming format.

TxPS/fTx,RxPS/fRx

Transmit Power Save, Receive Power Save (Pins 13,

11)

For a normal application, these output pins provide

the status of the internal power saving mode operation.

If the transmit channels counter circuitry is in power

down mode, TxPS/fTx outputs a high state. If the

receive-channels counter circuitry is in power down

mode, RxPS/fRx is set high. These output can be

applied for controlling the external power switch for

the transmitter and the receiver to save MCU control

pins. In the Tx/Rx channel counter test mode, the

TxPS/fTx and RxPS/fRx pins output the divided value of

the transmit channel counter (fTx) and the receive

channel counter (fRx), respectively. This test mode

operation is controlled by the control register. Details

of the counter test mode are in the Tx/Rx Channel

Counter Test section of this data sheet.

fin-T/fin-R

Transmit/Receive Counter Inputs (Pins14, 9)

fin-T and fin-R are inputs to the transmit and the

receive counters, respectively. These signals are

typically driven from the loop VCO and ac-coupled.

The minimum input signal level is 200mVp-p @

60.0MHz.

TxPDout/RxPDout

Transmit/Receive Phase detector Outputs (Pins15,

10)

These are three-state outputs of the transmit and

receive phase detectors for use as loop error signals

(see Figure7 for phase detector output waveforms).

Frequency fV > fR or fV leading: output=negative pulse.

Frequency fV < fR or fV lagging: output = positive pulse.

Frequency fV = fR and phase coincidence: output = high

impedance state.

fR is the divided-down reference frequency at the

phase detector input and fV is the divided-down VCO

frequency at the phase detector input.

LD Lock Detect (Pin16)

The lock detect signal is associated with the transmit

loop. The output at a high level indicates an out-of-

lock condition (see Figure 7 for the LD output

waveform).

VDD Positive Power Supply (Pin 12)

VDD is the most positive power supply potential

ranging from 2.5 to 5.5V with respect to VSS.

VSS Negative Power Supply (Pin 6)

VSS is the most negative supply potential and is

usually connected to ground.

A

OSC in

÷ N (12 bits)

f R1

B

÷4

OSC out

÷ M ( 14bits )

C

÷25

D

f R2

Crystal

11.150 MHz

11.150 MHz

10.240 MHz

¡ ÀN Value

446

223

512

fR1 ¡ æB

6.25 MHz

12.5 MHz

5.0 MHz

fR2 ¡ æC

1.0 MHz

12.000 MHz

600

5.0 MHz

Figure 6. Reference Frequencies for Cordless Phone

Applications of Various Countries

6

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