56F801 データシートの表示（PDF） - Motorola => Freescale

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56F801

16-bit Hybrid Controller

Motorola => Freescale 

Freescale Semiconductor, Inc.

DC Electrical Characteristics

Table 17. DC Electrical Characteristics (Continued)

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF

Characteristic

Symbol

Min

Typ Max Unit

PWM pin output sink current5

Input capacitance

Output capacitance

VDD supply current

Run7 (80MHz operation)

Run7 (60MHz operation)

Wait8

Stop

IOLP

CIN

COUT

IDDT6

16

— — mA

—

8

—

pF

—

12 —

pF

—

120 130 mA

—

102 111 mA

—

96 102 mA

—

62 70 mA

Low Voltage Interrupt, external power supply9

VEIO

2.4

2.7 3.0

V

Low Voltage Interrupt, internal power supply10

VEIC

2.0

2.2 2.4

V

Power on Reset11

VPOR

—

1.7 2.0

V

1. Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.

2. Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.

3. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

4. PWM pin output source current measured with 50% duty cycle.

5. PWM pin output sink current measured with 50% duty cycle.

6. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)

7. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports

configured as inputs; measured with all modules enabled.

8. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC

loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects

wait IDD; measured with PLL enabled.

9. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential

as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed

under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is

generated).

10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is

regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not

be generated unless the external power supply drops below the minimum specified value (3.0V).

11. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is

ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up

rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time

it self regulates.

56F801 Technical Data

15

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