ACS8522BT データシートの表示（PDF） - Semtech Corporation

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ACS8522BT

Synchronous Equipment Timing Source for Stratum 3/4E/4, SMC and Ethernet Systems

Semtech Corporation 

ACS8522BT eSETS

ADVANCED COMMS & SENSING

FINAL

DATASHEET

General Description

Overview

Please refer to Figure 1.

Both paths operate automatic or external source

selection. For automatic input reference selection, the T0

path has a more complex state machine than the T4 path.

The T0 and T4 PLL paths support the following common

features:

The ACS8522BT SETS device has four SEC clock inputs

(SEC1 to SEC4), and generates four output clocks on

outputs O1 to O4. The device offers a total of 55 possible

output frequencies. There are two independent paths

through the device:

T0 path comprising T0 DPLL and T0 output and feed-

back APLLs;

T4 path comprising T4 DPLL and T4 output APLL.

The T0 path is a high quality, highly configurable path

designed to provide features necessary for node timing

synchronization within a SONET/SDH network. The T4

path is a simpler and less configurable path designed to

give a totally independent route for internal equipment

synchronization. The device supports use of either or both

paths, locked together or independent.

The four SEC inputs ports are TTL/CMOS, 3 V and 5 V

compatible (with clamping if required by connecting the

VDD5V pin). Refer to Electrical Specifications for more

information on the electrical compatibility and details.

Input frequencies supported range from 2 kHz to

100 MHz.

 Automatic source selection according to input

priorities and quality level.

 Different quality levels (activity alarm thresholds) for

each input.

 Variable bandwidth, lock range and damping factor.

 Direct PLL locking to common SONET/SDH input

frequencies or any integer multiple of 8 kHz up to

100 MHz.

 Automatic mode switching between free-run, locked

and holdover states.

 Fast detection on input failure and entry into holdover

mode (holds at the last good frequency value).

 Frequency translation between input and output rates

via direct digital synthesis.

 High accuracy digital architecture for stable PLL

dynamics combined with an APLL for low jitter final

output clocks.

A number of features supported by the T0 path are not

supported by the T4 path, although these features can

also all be externally controlled by software. The

additional features of the T0 path are:

Common E1, DS1, OC3 and sub-divisions are supported

as spot frequencies to which the DPLLs will directly lock.

Any input frequency, up to 100 MHz, that is a multiple of

8 kHz can also be locked to via an inbuilt programmable

divider.

An input reference monitor is assigned to each of the four

inputs. The monitors operate continuously such that at all

times the status of all of the inputs to the device are

known. Each input can be monitored for both frequency

and activity, activity alone, or the monitors can be

disabled.

The frequency monitors have a “hard” (rejection) alarm

limit and a “soft” (flag only) alarm limit for monitoring

frequency, whilst the reference is still within its allowed

frequency band. Each input reference can be

programmed with a priority number allowing references to

be chosen according to the highest priority valid input. The

two paths (T0 and T4) have independent priorities to allow

completely independent operation of the two paths.

 Non-revertive mode.

 Phase build-out on source switch (hit-less source

switching).

 I/O phase offset control.

 Greater programmable bandwidth from 0.1 Hz to

70 Hz in 10 steps (the bandwidth of the T4 path is

programmable in 3 steps: 18 Hz, 35 Hz and 70 Hz).

 Noise rejection on low frequency input.

 Manual holdover frequency control.

 Controllable automatic holdover frequency filtering.

 Frame Sync pulse alignment.

The operation of the DPLL in the T0 path is controlled by

software or an internal state machine. The state machine

for the T4 path is very simple and cannot be

manually/externally controlled, however the overall

operation can be controlled by manual reference source

selection. An additional feature of the T4 path is the ability

to measure a phase difference between two inputs.

Revision 1.00/April 2010© Semtech Corp.

Page 9

www.semtech.com

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