AD5533ABC-1_ データシートの表示（PDF） - Analog Devices
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AD5533ABC-1_ Datasheet PDF : 16 Pages
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AD5532B
AC CHARACTERISTICS (VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V;
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications TMIN to TMAX, unless otherwise noted.)
Parameter1
DAC AC CHARACTERISTICS3
Output Voltage Settling Time
OFFS_IN Settling Time
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
AD5532B-1
B Version2
22
10
1
5
1
0.2
400
Unit
µs max
µs max
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
Conditions/Comments
500 pF, 5 kΩ Load Full-Scale Change
500 pF, 5 kΩ Load; 0 V to 3 V Step
1 LSB Change Around Major Carry
ISHA AC CHARACTERISTICS
Output Voltage Settling Time3
3
Acquisition Time
16
AC Crosstalk3
5
µs max
µs max
nV-s typ
Outputs Unloaded
NOTES
1See Terminology section.
2B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter1, 2
Limit at TMIN, TMAX
(B Version)
Unit
t1
0
t2
0
t3
50
t4
50
t5
20
t6
7
ns min
ns min
ns min
ns min
ns min
ns min
NOTES
1See Parallel Interface Timing Diagram.
2Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
Conditions/Comments
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
SERIAL INTERFACE
Parameter1, 2
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
fCLKIN3
14
t1
28
t2
28
t3
15
t4
50
t5
15
t6
5
t7
5
t84
20
t94
60
t10
400
t11
400
t125
7
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
DIN Setup Time
DIN Hold Time
SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback
SCLK Rising Edge to DOUT Valid
SCLK Falling Edge to DOUT High Impedance
10th SCLK Falling Edge to SYNC Falling Edge for Readback
24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write
SCLK Falling Edge to SYNC Falling Edge for Readback
NOTES
1See Serial Interface Timing Diagrams.
2Guaranteed by design and characterization, not production tested.
3In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4These numbers are measured with the load circuit of Figure 2.
5SYNC should be taken low while SCLK is low for readback.
Specifications subject to change without notice.
–4–
REV. A
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