AD9139(Rev0) データシートの表示（PDF） - Analog Devices

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AD9139
(Rev.:Rev0)

16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

Data Sheet

SYSTEM SETUP;

PROGRAM DAC INTERPOLATION MODES

AD9139

1. DAC HARDWARE RESET.

PULL THE DAC RESET PIN FROM HIGH TO LOW THEN BACK TO HIGH.

2. SET UP DAC INTERPOLATION MODE.

PROGRAM REG 0x28

3. RUN CLOCKS (DAC CLOCK, SYNC CLOCK, DCI, FRAME).

4. MAKE SURE DLL IS LOCKED IF IN DLL MODE, OR DELAY LINE IS ENABLED

AND PROPERLY CONFIGURED IF IN DELAY LINE MODE.

SET FIFO OFFSET TO 0

WRITE REG 0x23 = 0x00

ENABLE SYNC ENGINE

SET FRAME UPDATE MODE

REG 0x05[6:5] = 0b00

WRITE REG 0x21 = 0x01, IF RISING EDGE SYNC.

OR = 0x03, IF FALLING EDGE SYNC.

WRITE REG 0x22 = 0x18

IN THIS MODE, THE PART ONLY RESPONDS TO THE

FIRST VALID FRAME PULSE AND RESETS THE FIFO ONE TIME.

REG 0x05[6] = 0b1

WRITE REG 0x21 = 0x00

DISABLE SYNC

SYNC LOST/LOCK

FLAG BITS?

REG 0x05 [6:5] = 0b01

CALCULATE AND ADJUST

FIFO OFFSET

READ REG 0x05[6:5] ([SYNC_LOST;SYNC_LOCKED]).

IF THE SYNC-DAC SETUP/HOLD TIMES ARE NOT MET, THE SYNC MAY

NOT LOCK. CHANGE THE SYNC EDGE WHEN REENABLING THE SYNC

NEXT ROUND.

ADJUST FIFO OFFSET TO ACHIEVE THE OPTIMAL FIFO. LEVEL.

1. READ BACK REG 0x24. LET A = REG 0x24[6:4], B = REG 0x24[2:0].

2. LET X = INTERPOLATION RATE. (VALID NUMBERS ARE 1 AND 2).

3. OFFSET = (4 × X + 1) – (A × X + B)

4. IF OFFSET ≥ 0,

OFFSET = OFFSET.

ELSE

OFFSET = 8 × X + OFFSET.

5. LET A’ = FLOOR (OFFSET/X), B’ = OFFSET – (A’) × X

6. WRITE REG 0x23[6:4] = A’, REG 0x23[2:0] = B’.

7. SAVE A’ AND B’. (USE THE SAME A’ AND B’ VALUES WHEN

ADJUSTING THE FIFO OFFSET IN THE OTHER DACs).

REG 0x06[2:1] = 0b00

FIFO UF/OFF

LAG BITS?

REG 0x06[2:1] ≠ 0b00

FURTHER ADJUST FIFO OFFSET

READ REG 0x06[2:1].

IF NO FLAGS, SYNCHRONIZATION IS COMPLETE.

SKIP THE NEXT STEP.

IF EITHER BIT IS 1, FOLLOW THE NEXT STEP.

READ REG 0x23 AND RECORD IT AS RB1.

WRITE REG 0x23 = RB1 – 0x01;

READ REG 0x23 AND RECORD IT AS RB2.

WRITE REG 0x23 = RB2 + 0x01

WAKE UP DACs AND RUN

1. WAKE UP DACs

WRITE REG 0x01 = 0x00.

2. START DATA TRANSMISSION.

Figure 39. Synchronization Procedure Diagram

Rev. 0 | Page 31 of 56

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