AD9139(Rev0) データシートの表示（PDF） - Analog Devices
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AD9139 Datasheet PDF : 56 Pages
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AD9139
Data Sheet
DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTION
Table 21. Device Configuration Register Map
Reg Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x00 Common
[7:0] Reserved
SPI_LSB_
FIRST
DEVICE_RESET
Reserved
0x00 RW
0x01 PD_
CONTROL
[7:0] PD_DAC
Reserved
PD_DATARCV
Reserved
PD_DEVICE
PD_DACCLK PD_FRAME 0xC0 RW
0x03 INTERRUPT_
ENABLE0
[7:0] Reserved
ENABLE_
SYNC_LOST
ENABLE_
SYNC_
LOCKED
ENABLE_
SYNC_DONE
ENABLE_PLL_ ENABLE_PLL_
LOST
LOCKED
Reserved
0x00 RW
0x04 INTERRUPT_
ENABLE1
[7:0] ENABLE_
PARITY_FAIL
ENABLE_SED_
FAIL
ENABLE_DLL_ ENABLE_DLL_ Reserved
WARNING
LOCKED
ENABLE_FIFO_
UNDERFLOW
ENABLE_
FIFO_
OVERFLOW
Reserved
0x00 RW
0x05 INTERRUPT_
FLAG0
[7:0] Reserved
SYNC_LOST
SYNC_LOCKED SYNC_DONE PLL_LOST
PLL_LOCKED
Reserved
0x00 R
0x06 INTERRUPT_
FLAG1
[7:0] PARITY_
FAIL
SED_FAIL
DLL_
WARNING
DLL_LOCKED Reserved
FIFO_
UNDERFLOW
FIFO_
Reserved
OVERFLOW
0x00 R
0x07 IRQ_SEL0
[7:0] Reserved
SEL_SYNC_
LOST
SEL_SYNC_
LOCKED
SEL_SYNC_
DONE
SEL_PLL_LOST SEL_PLL_
LOCKED
Reserved
0x00 RW
0x08 IRQ_SEL1
[7:0] SEL_PARITY_
FAIL
SEL_SED_FAIL
SEL_DLL_
WARNING
SEL_DLL_
LOCKED
Reserved
FIFO_
UNDERFLOW
FIFO_
Reserved
OVERFLOW
0x00 RW
0x09 FRAME_MODE [7:0]
0x0A DATA_CNTR_0 [7:0]
0x0B DATA_CNTR_1 [7:0]
0x0C DATA_CNTR_2 [7:0]
0x0D DATA_CNTR_3 [7:0]
0x0E DATA_STAT_0 [7:0]
Reserved
PARUSAGE
FRMUSAGE
DLL_
ENABLE
DUTY_
CORRECTION_
EN
Reserved
CLEAR_WARN
Reserved
LOW_
DCI_EN
DLL_LOCK
Reserved
DLL_WARN
DLL_START_
WARNING
Reserved
DC_COUPLE_
LOW_EN
DLL_END_
WARNING
Reserved
Reserved
FRAME_PIN_USAGE
DLL_PHASE_OFFSET
Reserved
DCI_ON
Reserved
DLL_
RUNNING
0x00 RW
0x40 RW
0x39 RW
0x64 RW
0x06 RW
0x00 R
0x10 DACCLK_
RECEIVER_
CTRL
[7:0] DACCLK_
DUTYCYCLE_
CORRECTION
Reserved
DACCLK_
CROSSPOINT_
CTRL_ENABLE
DACCLK_CROSSPOINT_LEVEL
0xFF RW
0x11 REFCLK_
[7:0] DUTYCYCLE_
RECEIVER_CTRL
CORRECTION
Reserved
REFCLK_
CROSSPOINT_
CTRL_ENABLE
REFCLK_CROSSPOINT_LEVEL
0x5F RW
0x12 PLL_CTRL0
[7:0] PLL_ENABLE
AUTO_MANUAL_
SEL
PLL_MANUAL_BAND
0x00 RW
0x14 PLL_CTRL2
[7:0]
PLL_LOOP_BW
PLL_CP_CURRENT
0xE7 RW
0x15 PLL_CTRL3
[7:0]
DIGLOGIC_DIVIDER
Reserved
CROSSPOINT_
CTRL_EN
VCO_DIVIDER
LOOP_DIVIDER
0xC9 RW
0x16 PLL_STATUS0 [7:0] PLL_LOCK
Reserved
VCO_CTRL_VOLTAGE_READBACK
0x00 R
0x17 PLL_STATUS1 [7:0]
Reserved
PLL_BAND_READBACK
0x00 R
0x18 DAC_FS_ADJ0 [7:0]
DAC_FULLSCALE_ADJUST_LSB
0xF9 RW
0x19 DAC_FS_ADJ1 [7:0]
BG_TRIM
RESERVED
DAC_FULLSCALE_ADJUST_ 0xE1 RW
MSB
0x1C DIE_TEMP_ [7:0] Reserved
SENSOR_CTRL
FS_CURRENT
REF_CURRENT
DIE_TEMP_ 0x02 RW
SENSOR_EN
0x1D DIE_TEMP_LSB [7:0]
DIE_TEMP_LSB
0x00 R
0x1E DIE_TEMP_MSB [7:0]
DIE_TEMP_MSB
0x00 R
0x1F CHIP_ID
[7:0]
CHIP_ID
0x0A R
0x20 INTERRUPT_ [7:0]
CONFIG
INTERRUPT_CONFIGURATION
0x00 RW
0x21 SYNC_CTRL [7:0]
Reserved
SYNC_CLK_ SYNC_
EDGE_SEL ENABLE
0x00 RW
0x22 FRAME_RST_
CTRL
0x23 FIFO_LEVEL_
CONFIG
0x24 FIFO_LEVEL_
READBACK
[7:0]
[7:0] Reserved
[7:0] Reserved
Reserved
INTEGER_FIFO_LEVEL_REQUEST
INTEGER_FIFO_LEVEL_READBACK
ARM_FRAME
Reserved
Reserved
EN_CON_
FRAME_RESET
FRAME_RESET_MODE
FRACTIONAL_FIFO_LEVEL_REQUEST
FRACTIONAL_FIFO_LEVEL_READBACK
0x12 RW
0x40 RW
0x00 R
0x25 FIFO_CTRL
[7:0]
Reserved
FIFO_SPI_
RESET_ACK
FIFO_SPI_
RESET_
REQUEST
0x00 RW
0x26 DATA_
[7:0] DATA_
FORMAT_SEL
FORMAT
Reserved
DATA_BUS_ 0x00 RW
WIDTH
0x27 DATAPATH_
CTRL
[7:0] INVSINC_
ENABLE
Reserved
DIG_GAIN_
DCOFFSET_
ENABLE
Reserved
0x00 RW
Rev. 0 | Page 40 of 56
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