AD9510(RevB) データシートの表示（PDF） - Analog Devices

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AD9510
(Rev.:RevB)

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Analog Devices 

AD9510

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs .................................................................................. 5

Clock Outputs ............................................................................... 6

Timing Characteristics ................................................................ 6

Clock Output Phase Noise .......................................................... 8

Clock Output Additive Time Jitter........................................... 11

PLL and Distribution Phase Noise and Spurious................... 13

Serial Control Port ..................................................................... 13

FUNCTION Pin ......................................................................... 14

STATUS Pin ................................................................................ 14

Power............................................................................................ 15

Timing Diagrams............................................................................ 16

Absolute Maximum Ratings.......................................................... 17

Thermal Characteristics ............................................................ 17

ESD Caution................................................................................ 17

Pin Configuration and Function Descriptions........................... 18

Typical Performance Characteristics ........................................... 20

Terminology .................................................................................... 24

Typical Modes of Operation.......................................................... 25

PLL with External VCXO/VCO Followed by Clock

Distribution ................................................................................. 25

Clock Distribution Only............................................................ 25

PLL with External VCO and Band-Pass Filter Followed by

Clock Distribution...................................................................... 26

Functional Description .................................................................. 28

REVISION HISTORY

9/13—Rev. A to Rev. B

Changes to General Description Section ...................................... 1

Changes to Table 4............................................................................ 6

Changes to Table 6.......................................................................... 11

Added Table 13; Renumbered Sequentially ................................ 17

Changes to Figure 6........................................................................ 18

Added EPAD Row, Table 14 .......................................................... 19

Changes to Figure 21...................................................................... 22

Overall ......................................................................................... 28

PLL Section ................................................................................. 28

FUNCTION Pin ......................................................................... 32

Distribution Section................................................................... 32

CLK1 and CLK2 Clock Inputs.................................................. 32

Dividers........................................................................................ 32

Delay Block ................................................................................. 37

Outputs ........................................................................................ 37

Power-Down Modes .................................................................. 38

Reset Modes ................................................................................ 38

Single-Chip Synchronization.................................................... 39

Multichip Synchronization ....................................................... 39

Serial Control Port ......................................................................... 40

Serial Control Port Pin Descriptions ....................................... 40

General Operation of Serial Control Port............................... 40

The Instruction Word (16 Bits) ................................................ 41

MSB/LSB First Transfers ........................................................... 41

Register Map and Description ...................................................... 44

Summary Table ........................................................................... 44

Register Map Description ......................................................... 46

Power Supply................................................................................... 53

Power Management ................................................................... 53

Applications Information .............................................................. 54

Using the AD9510 Outputs for ADC Clock Applications.... 54

CMOS Clock Distribution ........................................................ 54

LVPECL Clock Distribution ..................................................... 55

LVDS Clock Distribution .......................................................... 55

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 55

Outline Dimensions ....................................................................... 56

Ordering Guide .......................................................................... 56

Changes to Delay Block Section, Figure 40, and Calculating the

Delay Section................................................................................... 37

Changes to Address 0x36[5:1] and Address 0x3A[5:1],

Table 24 ............................................................................................ 44

Changes to Address 0x36 and Address 0x3A, Table 25............. 49

Updated Outline Dimensions ....................................................... 56

Changes to Ordering Guide .......................................................... 56

Rev. B | Page 2 of 56

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