AD9510(RevB) データシートの表示（PDF） - Analog Devices

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AD9510
(Rev.:RevB)

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Analog Devices 

Data Sheet

AD9510

Parameter

PROPAGATION DELAY, CLK-TO-LVDS OUT1

OUT4, OUT5, OUT6, OUT7

Divide = Bypass

Divide = 2 − 32

Variation with Temperature

OUTPUT SKEW, LVDS OUTPUTS

OUT4 to OUT7 on Same Part2

OUT5 to OUT6 on Same Part2

All LVDS OUTs on Same Part2

All LVDS OUTs Across Multiple Parts3

Same LVDS OUT Across Multiple Parts3

CMOS

Output Rise Time

Output Fall Time

PROPAGATION DELAY, CLK-TO-CMOS OUT1

Divide = Bypass

Divide = 2 − 32

Variation with Temperature

OUTPUT SKEW, CMOS OUTPUTS

All CMOS OUTs on Same Part2

All CMOS OUTs Across Multiple Parts3

Same CMOS OUT Across Multiple Parts3

LVPECL-TO-LVDS OUT

Output Skew

LVPECL-TO-CMOS OUT

Output Skew

LVDS-TO-CMOS OUT

Output Skew

DELAY ADJUST4

Shortest Delay Range5

Zero Scale

Full Scale

Linearity, DNL

Linearity, INL

Longest Delay Range5

Zero Scale

Full Scale

Linearity, DNL

Linearity, INL

Delay Variation with Temperature

Long Delay Range, 8 ns6

Zero Scale

Full Scale

Short Delay Range, 1 ns6

Zero Scale

Full Scale

Symbol

tLVDS

tSKV

tSKV

tSKV

tSKV_AB

tSKV_AB

tRC

tFC

tCMOS

tSKC

tSKC_AB

tSKC_AB

tSKP_V

tSKP_C

tSKV_C

Min

0.99

1.04

−85

−175

−175

1.02

1.07

−140

0.74

0.88

158

0.05

0.57

0.20

7.0

Typ

1.33

1.38

0.9

681

646

1.39

1.44

1

+145

0.92

1.14

353

0.36

0.95

0.5

0.8

0.57

8.0

0.3

0.6

0.35

−0.14

0.51

0.67

Max

1.59

1.64

+270

+155

+270

450

325

865

992

1.71

1.76

+300

650

500

1.14

1.43

506

0.68

1.32

0.95

9.2

Unit

ns

ns

ps/°C

ps

ps

ps

ps

ps

ps

ps

ns

ns

ps/°C

ps

ps

ps

ns

ns

ps

ns

ns

LSB

LSB

ns

ns

LSB

LSB

ps/°C

ps/°C

ps/°C

ps/°C

Test Conditions/Comments

Delay off on OUT5 and OUT6

Delay off on OUT5 and OUT6

B outputs are inverted, termination = open

20% to 80%; CLOAD = 3 pF

80% to 20%; CLOAD = 3 pF

Delay off on OUT5 and OUT6

Delay off on OUT5 and OUT6

Everything the same; different logic type

LVPECL to LVDS on same part

Everything the same; different logic type

LVPECL to CMOS on same part

Everything the same; different logic type

LVDS to CMOS on same part

OUT5 (OUT6); LVDS and CMOS

Register 0x35, Register 0x39[5:1] = 11111b

Register 0x36, Register 0x3A[5:1] = 00000b

Register 0x36, Register 0x3A[5:1] = 11000b

Register 0x35, Register 0x39[5:1] = 00000b

Register 0x36, Register 0x3A[5:1] = 00000b

Register 0x36, Register 0x3A[5:1] = 11000b

1 These measurements are for CLK1. For CLK2, add approximately 25 ps.

2 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.

3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

4 The maximum delay that can be used is a little less than one half the period of the clock. A longer delay disables the output.

5 Incremental delay; does not include propagation delay.

6 All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. B | Page 7 of 56

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