AD9925 データシートの表示（PDF） - Analog Devices

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AD9925

CCD Signal Processor with Vertical Driver and Precision Timing ™ Generator

Analog Devices 

AD9925

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9925 generates high speed timing signals using the flexi-

ble Precision Timing core. This core is the foundation that gen-

erates the timing used for both the CCD and the AFE: the reset

gate (RG), horizontal drivers H1 to H4, and the SHP/SHD sample

clocks. The unique architecture provides precise control over

the horizontal CCD readout and the AFE correlated double sam-

pling, allowing the system designer to optimize image quality.

The high speed timing of the AD9925 operates the same in

either master or slave mode configuration. For more informa-

tion on synchronization and pipeline delays, see the Power-Up

and Synchronization section.

Timing Resolution

The Precision Timing core uses a 13 master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 17 illustrates how the internal timing

core divides the master clock period into 48 steps or edge posi-

tions. Using a 20 MHz CLI frequency, the edge resolution of the

Precision Timing core is 1 ns. If a 1× system clock is not avail-

able, it is also possible to use a 2× reference clock by program-

ming the CLIDIVIDE register (Addr x30). The AD9925 will

then internally divide the CLI frequency by two.

The AD9925 also includes a master clock output, CLO, which is

the inverse of CLI. This output can be used as a crystal driver. A

crystal can be placed between the CLI and CLO pins to generate

the master clock for the AD9925. For more information on

using a crystal, see Figure 72.

High Speed Clock Programmability

Figure 18 shows how the high speed clocks RG, H1 to H4, SHP,

and SHD are generated. The RG pulse has programmable rising

and falling edges and may be inverted using the polarity control.

The horizontal clocks, H1 and H3, have programmable rising

and falling edges and polarity control. The H2 and H4 clocks

are always inverses of H1 and H3, respectively. Table 8 summa-

rizes the high speed timing registers and their parameters.

Figure 19 shows the typical 2-phase H-clock arrangement in

which H3 and H4 are programmed for the same edge location

as H1 and H2.

The edge location registers are 6 bits wide, but there are only

48 valid edge locations available. Therefore, the register values

are mapped into four quadrants, with each quadrant containing

12 edge locations. Table 9 shows the correct register values for

the corresponding edge locations.

POSITION

P[0]

CLI

tCLIDLY

1 PIXEL

PERIOD

P[12]

P[24]

P[36]

P[48] = P[0]

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY = 6ns TYP).

Figure 17. High Speed Clock Resolution from CLI Master Clock Input

Rev. A | Page 15 of 96

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