AD9925 データシートの表示（PDF） - Analog Devices

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AD9925

CCD Signal Processor with Vertical Driver and Precision Timing ™ Generator

Analog Devices 

AD9925

CCD

SIGNAL

RG

H1/H3

H2/H4

NOTE

1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.

Figure 19. 2-Phase H-Clock Operation

Table 9. Precision Timing Edge Locations

Quadrant

Edge Location (Dec)

I

0 to 11

II

12 to 23

III

24 to 35

IV

36 to 47

Register Value (Dec)

0 to 11

16 to 27

32 to 43

48 to 59

Register Value (Bin)

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

POSITION

PIXEL

PERIOD

RG

H1/H3

P[0]

RGr[0]

Hr[0]

P[12]

RGf[12]

P[24]

Hf[24]

P[36]

P[48] = P[0]

H2/H4

CCD

SIGNAL

SHP[24]

tS1

SHD[48]

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

Figure 20. High Speed Timing Default Locations

Rev. A | Page 17 of 96

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