AD9925 データシートの表示（PDF） - Analog Devices

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AD9925

CCD Signal Processor with Vertical Driver and Precision Timing ™ Generator

Analog Devices 

AD9925

P[0]

PIXEL

PERIOD

P[12]

P[24]

P[36]

P[48] = P[0]

DCLK

tOD

DOUT

NOTES

1. DATA OUTPUT (DOUT) AND DCLK PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

3. OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

Figure 21. Digital Output Phase Adjustment

CLI

tCLIDLY

N– 1

N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 N + 11 N + 12 N + 13

CCDIN

SHD

(INTERNAL)

SAMPLE PIXEL N

ADC DOUT

(INTERNAL)

DCLK

N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1

N

N+1 N+2

tDOUTINH

DOUT

PIPELINE LATENCY = 11 CYCLES

N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1

N

N+1 N+2

NOTES

1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY tDOUTINH, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT THE

11 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED FOR THE DOUTPHASE LOCATION.

4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.

5. RECOMMENDED VALUE FOR tOD (DOUT DLY) IS 4ns.

6. THE DOUT LATCH CAN BE BYPASSED USING REGISTER 0x03, BIT [4] = 1, SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT THE

DOUT PINS. THIS CONFIGURATION IS RECOMMENDED IF ADJUSTABLE DOUT PHASE IS NOT REQUIRED.

Figure 22. Digital Data Output Pipeline Delay

HORIZONTAL CLAMPING AND BLANKING

The AD9925’s horizontal clamping and blanking pulses are fully

programmable to suit a variety of applications. Individual con-

trol is provided for CLPOB, PBLK, and HBLK during the differ-

ent regions of each field. This allows the dark pixel clamping

and blanking patterns to be changed at each stage of the read-

out, which accommodates the different image transfer timing

and high speed line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as

shown in Figure 23. These two signals are independently pro-

grammed using the registers in Table 10. SPOL is the start po-

larity for the signal, and TOG1 and TOG2 are the first and sec-

ond toggle positions of the pulse. Both signals are active low

and should be programmed accordingly.

A separate pattern for CLPOB and PBLK may be programmed

for every 10 vertical sequences. As described in the Vertical

Timing Generation section, up to 10 separate vertical sequences

can be created, each containing a unique pulse pattern for

CLPOB and PBLK. Figure 37 shows how the sequence change

positions divide the readout field into different regions. A dif-

ferent vertical sequence can be assigned to each region, allowing

the CLPOB and PBLK signals to be changed accordingly with

each change in the vertical timing.

CLPOB Masking Area

Additionally, the AD9925 allows the CLPOB signal to be dis-

abled during certain lines in the field without changing any of

the existing CLPOB pattern settings. There are two ways to use

CLPOB masking. First, the six CLPOBMASK registers can be used

Rev. A | Page 18 of 96

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