AD9937 データシートの表示（PDF） - Analog Devices

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AD9937

CCD Signal Processor with Precision Timing™ Generator

Analog Devices 

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9937 AFE signal processing chain is shown in Figure 11.

Each processing step is essential in achieving a high quality image

from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1 µF series coupling

capacitor. This restores the dc level of the CCD signal to approxi-

mately 1.5 V to be compatible with the 3 V analog supply of

the AD9937.

AD9937

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

diagram in Figure 13 illustrates how the two internally gener-

ated CDS clocks, SHP and SHD, are used to sample the

reference level and the data level, respectively, of the CCD

signal. The placement of the SHP and SHD sampling edges is

determined by the setting of the SHPLOC (addr 0x05) and

SHDLOC (addr 0x05) control registers. Placement of these two

clock edges is critical in achieving the best performance from

the CCD.

0.1␮F

CCDIN

DC RESTORE

1.5V

SHPSHD

CDS

AD9937

6dB TO 40dB

VGA

REFB

1.0V

1.0␮F

1.0␮F

REFT

2.0V

INTERNAL

VREF

2V FULL

SCALE

ADC

DOUT

PHASE

OUTPUT 10

DATA

LATCH

DOUT

10

VGA GAIN

REGISTER

DOUT

SHP SHD PHASE

PRECISION

TIMING

GENERATION

8-BIT

DAC

OPTICAL BLACK

CLAMP

DIGITAL

FILTER

CLPOB

8

CLPOB

CLAMP LEVEL

REGISTER

V-H

TIMING

GENERATION

Figure 11. AFE Block Diagram

REV. 0

–21–

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