AD9937 データシートの表示（PDF） - Analog Devices

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AD9937

CCD Signal Processor with Precision Timing™ Generator

Analog Devices 

12-BIT

HD COUNTER

AD9937

PBLK

1

2

3

4

PROGRAMMABLE CLOCK POSITIONS

1. PBLKTOG1 (PROGRAMMABLE AT MODE_REG(9))

2. PBLKTOG2 (PROGRAMMABLE AT MODE_REG(9))

3. PBLKTOG3 (PROGRAMMABLE AT MODE_REG(10))

4. PBLKTOG4 (PROGRAMMABLE AT MODE_REG(10))

Figure 19. PBLK Timing

12-BIT

HD COUNTER

HDLEN = 1500

PBLKTOG1 = 500

PBLKTOG2 = 785

PBLK

1. PBLKTOG1 = 500

2. PBLKTOG2 = 785

3. PBLKTOG3 = 4095

4. PBLKTOG4 = 4095

5. THIS PBLK PULSE SEQUENCE IS USED IN THE EXAMPLE BELOW.

11-BIT

VD COUNTER

N–4

N–3

N–2

N–1

N

VD

500 785

500 785

500

12-BIT

HD COUNTER

000

001

002

003

500 785

500 785

500 785

PBLKSTART

PBLKSTOP

1. PBLKSTART = N – 2

2. PBLKSTOP = 001

3. THIS EXAMPLE SHOWS HOW PBLK IS LOW IN THE VERTICAL BLANKING REGION FROM PBLKTOG1 IN LINE PBLKSTART UNTIL PBLKTOG2 IN LINE PBLKSTOP.

AS SHOWN IN THE ABOVE FIGURE, PBLK REMAINS LOW FROM PBLKTOG1 TO PBLKTOG2.

Figure 20. Example of PBLK Applied in Vertical Blanking Region Using PBLKSTART and PBLKSTOP Registers

REV. 0

–27–

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