ADN2805(Rev0) データシートの表示（PDF） - Analog Devices

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ADN2805
(Rev.:Rev0)

1.25 Gbps Clock and Data Recovery IC

Analog Devices 

The gain of the loop integrator is small for high jitter

frequencies; therefore, larger phase differences are needed to

make the loop control voltage large enough to tune the range of

the phase shifter. Large phase errors at high jitter frequencies

cannot be tolerated. In this region, the gain of the integrator

determines the jitter accommodation. Because the gain of the

loop integrator declines linearly with frequency, jitter accom-

modation is lower with higher jitter frequency. At the highest

frequencies, the loop gain is very small, and little tuning of the

ADN2805

phase shifter can be expected. In this case, jitter accommodation is

determined by the eye opening of the input data, the static

phase error, and the residual loop jitter generation. The jitter

accommodation is roughly 0.5 UI in this region. The corner

frequency between the declining slope and the flat region is

the closed loop bandwidth of the delay-locked loop, which is

roughly 1.5 MHz at 1.25 Gbps.

Rev. 0 | Page 11 of 16

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