ADT7473ARQZ データシートの表示（PDF） - Analog Devices
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ADT7473ARQZ Datasheet PDF : 76 Pages
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ADT7473
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
Min
Typ
Max
2.0
3.6
Unit Test Conditions/Comments
V
V
Maximum input voltage
Input Low Voltage, VIL
Hysteresis
0.8
−0.3
0.5
V
V
V p-p
Minimum input voltage
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Detect Clock Low Timeout, tTIMEOUT
0.75 × VCC V
0.4
V
±1
µA
VIN = VCC
±1
µA
VIN = 0
5
pF
See Figure 2
10
400
kHz
50
ns
4.7
µs
4.7
µs
4.0
50
µs
1,000
ns
300
µs
250
ns
15
35
ms Can be optionally disabled
1 All voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA = 25°C and represent most likely parametric norm. Logic inputs accept input
high voltages up to VMAX, even when device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a
rising edge.
TIMING DIAGRAM
Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested.
SCL
tR
tLOW
tHD; STA
tHD; DAT
SDA
tBUF
P
S
tF
tHIGH
tSU; DAT
tHD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
Rev. A | Page 5 of 76
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