AT25P1024C1-10CI-2.7_06 データシートの表示（PDF） - Atmel Corporation
部品番号
コンポーネント説明
メーカー
AT25P1024C1-10CI-2.7_06 Datasheet PDF : 17 Pages
| |||
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• 2.1 MHz Clock Rate
• 128-byte Page Mode Only for Write Operations
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• Self-Timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >40 Years
• 20-lead JEDEC SOIC and 8-lead Leadless Array Package
SPI Serial
EEPROMs
1M (131,072 x 8)
Description
The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable
read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT25P1024 is available in space saving
20-lead JEDEC SOIC and 8-lead LAP packages.
AT25P1024
Note:
Not Recommended for new
design; Please refer to
AT25FS010 datasheet.
Table 1. Pin Configurations
Pin Name Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC
No Connect
20-lead SOIC
CS 1
SO 2
NC 3
NC 4
NC 5
NC 6
NC 7
NC 8
WP 9
GND 10
20 VCC
19 HOLD
18 NC
17 NC
16 NC
15 NC
14 NC
13 NC
12 SCK
11 SI
8-lead Leadless Array
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
The AT25P1024 is enabled through the Chip Select pin (CS) and accessed via a 3-
wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-timed, and no separate
erase cycle is required before write.
1082I–SEEPR–7/06
1
Share Link: 