ATF-54143 データシートの表示（PDF） - HP => Agilent Technologies

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ATF-54143

Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plastic Package

HP => Agilent Technologies 

The values of resistors R1 and R2

are calculated with the following

formulas

R1 = Vgs (2)

Ip

BB

R2 = (Vds – Vgs) R1 (3)

Vgs

p

Example Circuit

VDD = 5 V

Vds = 3V

Ids = 60 mA

Vgs = 0.59V

Choose IBB to be at least 10X the

normal expected gate leakage

current. IBB was chosen to be

2 mA for this example. Using

equations (1), (2), and (3) the

resistors are calculated as

follows

R1 = 295Ω

R2 = 1205Ω

R3 = 32.3Ω

Active Biasing

Active biasing provides a means

of keeping the quiescent bias

point constant over temperature

and constant over lot to lot

variations in device dc perfor-

mance. The advantage of the

active biasing of an enhancement

mode PHEMT versus a depletion

mode PHEMT is that a negative

power source is not required. The

techniques of active biasing an

enhancement mode device are

very similar to those used to bias

a bipolar junction transistor.

INPUT

Zo

C1

Q1

L1

L2

C2

R5

C3

R6

C7

Q2

R7

R1

C4

OUTPUT

Zo

L4

L3

C5

R4

C6

Vdd

R3

R2

Figure 2. Typical ATF-54143 LNA with

Active Biasing.

An active bias scheme is shown

in Figure 2. R1 and R2 provide a

constant voltage source at the

base of a PNP transistor at Q2.

The constant voltage at the base

of Q2 is raised by 0.7 volts at the

emitter. The constant emitter

voltage plus the regulated VDD

supply are present across resis-

tor R3. Constant voltage across

R3 provides a constant current

supply for the drain current.

Resistors R1 and R2 are used to

set the desired Vds. The com-

bined series value of these

resistors also sets the amount of

extra current consumed by the

bias network. The equations that

describe the circuit’s operation

are as follows.

VE = Vds + (Ids • R4) (1)

R3 = VDD – VE

(2)

Ids p

VB = VE – VBE

(3)

R1

VB = R1 + R2p VDD

(4)

and rearranging equation (5)

provides the following formula

R1 =

VDD

9 (5A)

( ) IBB

1 + VDD – VB p

VB

Example Circuit

VDD = 5V

Vds = 3V

Ids = 60 mA

R4 = 10Ω

VBE = 0.7 V

Equation (1) calculates the

required voltage at the emitter of

the PNP transistor based on

desired Vds and Ids through

resistor R4 to be 3.6V. Equation

(2) calculates the value of resis-

tor R3 which determines the

drain current Ids. In the example

R3 = 23.3Ω. Equation (3) calcu-

lates the voltage required at the

junction of resistors R1 and R2.

This voltage plus the step-up of

the base emitter junction deter-

mines the regulated Vds. Equa-

tions (4) and (5) are solved

simultaneously to determine the

value of resistors R1 and R2. In

the example R1=1450Ω and

R2 =1050Ω. R7 is chosen to be

1kΩ. This resistor keeps a small

amount of current flowing

through Q2 to help maintain bias

stability. R6 is chosen to be

10kΩ. This value of resistance is

necessary to limit Q1 gate

current in the presence of high

RF drive level (especially when

Q1 is driven to P1dB gain com-

pression point).

VDD = IBB (R1 + R2) (5)

Rearranging equation (4)

provides the following formula

R2 = R1 (VDD – VB) (4A)

VB

p

11

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