MBRS340 データシートの表示（PDF） - Linear Technology

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MBRS340

42V, 2.5A, 2MHz Step-Down Switching Regulator with 2.7µA Quiescent Current

Linear Technology 

LT3975

APPLICATIONS INFORMATION

Enable and Undervoltage Lockout

The LT3975 is in shutdown when the EN pin is low and

active when the pin is high. The falling threshold of the

EN comparator is 1.02V, with 60mV of hysteresis. The EN

pin can be tied to VIN if the shutdown feature is not used.

Undervoltage lockout (UVLO) can be added to the LT3975

as shown in Figure 6. Typically, UVLO is used in situa-

tions where the input supply is current limited, or has a

relatively high source resistance. A switching regulator

draws constant power from the source, so source cur-

rent increases as source voltage drops. This looks like a

negative resistance load to the source and can cause the

source to current limit or latch low under low source voltage

conditions. UVLO prevents the regulator from operating

at source voltages where the problems might occur. The

UVLO threshold can be adjusted by setting the values R3

and R4 such that they satisfy the following equation:

VUVLO

=

VEN(THRESH)





R3 +R4

R4 

where VEN(THRESH) is the falling threshold of the EN pin,

which is approximately 1.02V, and where switching should

stop when VIN falls below VUVLO. Note that due to the

comparator’s hysteresis, switching will not start until the

input is about 6% above VUVLO.

When operating in Burst Mode operation for light load

currents, the current through the UVLO resistor network

can easily be greater than the supply current consumed

by the LT3975. Therefore, the UVLO resistors should be

large to minimize their effect on efficiency at low loads.

VIN

LT3975

R3

1.02V +

EN

–

R4

SHDN

LT3975 F06

Figure 6. Undervoltage Lockout

Soft-Start

The SS pin can be used to soft start the LT3975 by throt-

tling the maximum input current during start-up and reset.

An internal 1.8μA current source charges an external

capacitor generating a voltage ramp on the SS pin. The

SS pin clamps the internal VC node, which slowly ramps

up the current limit. Maximum current limit is reached

when the SS pin is about 1.5V or higher. By selecting a

large enough capacitor, the output can reach regulation

without overshoot. Figure 7 shows start-up waveforms

for a typical application with a 10nF capacitor on SS for

a 1.65Ω load when the EN pin is pulsed high for 7ms.

The external SS capacitor is actively discharged when

the EN pin is low, or during thermal shutdown. The active

pull-down on the SS pin has a resistance of about 150Ω.

IL

1A/DIV

VOUT

1V/DIV

VSS

0.5V/DIV

1ms/DIV

3975 F07

Figure 7. Soft-Start Waveforms for the Front-Page Application

with a 10nF Capacitor on SS. EN Is Pulsed High for About 7ms

with a 1.65Ω Load Resistor

Synchronization

To select low ripple Burst Mode operation, tie the SYNC

pin below 0.5V (this can be ground or a logic output).

Synchronizing the LT3975 oscillator to an external fre-

quency can be done by connecting a square wave (with

20% to 80% duty cycle) to the SYNC pin. The square

wave amplitude should have valleys that are below 0.5V

and peaks above 1.5V (up to 6V).

The LT3975 will pulse skip at low output loads while syn-

chronized to an external clock to maintain regulation. At

very light loads, the part will go to sleep between groups of

pulses, so the quiescent current of the part will still be low,

but not as low as in Burst Mode operation. The quiescent

current in a typical application when synchronized with an

external clock is 11µA at no load. Holding the SYNC pin

DC high yields no advantages in terms of output ripple or

minimum load to full frequency, so is not recommended.

Never float the SYNC pin.

3975f

19

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