MAX121C データシートの表示（PDF） - Maxim Integrated
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MAX121C Datasheet PDF : 26 Pages
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MAX121
308ksps ADC with DSP Interface and 78dB SINAD
Pin Configurations
TOP VIEW
+
1 VSS
MODE 16
2 VDD
CS 15
MAX121
3 AIN
CLKIN 14
4 VREF
5 AGND
CONVST 13
SCLK 12
6 INVCLK SDATA 11
7 INVFRM FSTRT 10
8 DGND
SFRM 9
PDIP/SO
VSS 1
VDD 2
AIN 3
VREF 4
N.C. 5
N.C. 6
AGND 7
INVCLK 8
INVFRM 9
DGND 10
+
MAX121
SSOP
20 MODE
19 CS
18 CLKIN
17 CONVST
16 N.C.
15 N.C.
14 SCLK
13 SDATA
12 FSTRT
11 SFRM
Pin Description
PIN
PDIP/SO
SSOP
1
1
2
2
3
3
4
4
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
17
14
18
15
19
16
20
—
5, 6, 15, 16
NAME
FUNCTION
VSS
VDD
AIN
VREF
AGND
INVCLK
INVFRM
DGND
SFRM
FSTRT
SDATA
SCLK
CONVST
CLKIN
CS
MODE
N.C.
Negative Power Supply, -12V or -15V. Bypass to AGND with 10µF and 0.1µF capacitors.
Positive Power Supply, +5V. Bypass to AGND with 10µF and 0.1µF capacitors.
Sampling Analog Input, ±5V Bipolar Input Range
-5V Reference Output. Bypass to AGND with 22µF || 0.1µF capacitors.
Analog Ground
Invert Serial Clock. Connect to DGND to invert the SCLK output (relative to CLKIN).
Invert Serial Frame. This input sets the polarity of the SFRM output as follows:
If INVFRM = DGND, SFRM is high during a conversion.
If INVFRM = VDD, SFRM is low during a conversion.
Digital Ground
Serial Frame Output. Normally high (INVFRM = VDD), falls at the beginning of the
conversion and rises at the end (after 16 tCLK) signaling the end of a 16-bit frame.
Frame Start Output. High pulse that lasts one clock cycle, falling edge indicates that a valid
MSB is available.
Serial Data Output. MSB first, two’s-complement binary output code.
Serial Clock Output. Same polarity as CLKIN if INVCLK = VDD, inverted CLKIN if
INVCLK = DGND. Note that SCLK runs whenever CLKIN is active.
Active-Low Convert Start Input. Conversions are initiated on falling edges.
Clock Input. Supply at TTL-/CMOS-compatible clock from 0.1MHz to 5.5MHz, 40% to 60%
duty cycle.
Active-Low Chip Select Input. CS = DGND enables the three-state outputs. Also, if
CONVST is low, initiates a conversion on the falling edge of CS.
Hardwire to set operational mode. VDD (single conversions),
DGND (continuous conversions).
No Connection. Not internally connected.
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