MAX121C データシートの表示（PDF） - Maxim Integrated

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MAX121C

308ksps ADC with DSP Interface and 78dB SINAD

Maxim Integrated 

MAX121

308ksps ADC with DSP Interface and 78dB SINAD

AGND

-12V/-15V

0.1µF

10µF

+5V

ANALOG

INPUT

10µF

AGND

0.1µF

0.1µF

AGND

22µF

VDD

VSS

MODE

VDD

CS

MAX121

AIN

CLKIN

VREF

CONVST

AGND

SCLK

INVCLK SDATA

INVFRM FSTRT

DGND

CLOCK

INPUT

DGND

TO

SERIAL

PORT

DGND

DGND

Figure 1. MAX121 in the Simplest Operational Mode

(Continuous-Conversion Mode)

Detailed Description

ADC Operation

The MAX121 uses successive approximation and input

track/hold (T/H) circuitry to convert an analog signal to a

14-bit serial digital output code. The control logic interfac-

es easily to most microprocessors (µPs) and digital­signal

processors (DSPs), requiring only a few passive com-

ponents for most applications. The T/H does not require

an external capacitor. Figure 1 shows the MAX121 in its

simplest operational configuration.

Analog Input Track/Hold

The Equivalent Input Circuit (Figure 2) illustrates the

sampling architecture of the ADC’s analog comparator.

An internal buffer charges the hold capacitor to minimize

the required acquisition time between conversions. The

analog input appears as a 6kΩ resistor in parallel with a

10pF capacitor.

Between conversions, the buffer input is connected to AIN

through the input resistance. When a conversion starts,

the buffer input is disconnected from AIN, thus sampling

the input. At the end of the conversion, the buffer input

is reconnected to AIN, and the hold capacitor tracks the

input voltage.

The T/H is in its tracking mode whenever a conversion is

not in progress. Hold mode starts approximately 10ns after

AIN

CPACKAGE

10pF

VREF

3kΩ

3kΩ

TRACK

HOLD

VREF

(-5V)

DAC

BUFFER CHOLD

7pF

CSWITCH

2pF

SAMPLING

COMPARATOR

SAR

Figure 2. Equivalent Input Circuit

a conversion is initiated (aperture delay). The variation in

this delay from one conversion to the next (aperture jitter)

is typically 30ps. Figures 7–9 detail the track/hold mode

and interface timing for the three different interface modes.

lntemal Reference

The MAX121 -5.00V buried-zener reference biases the

internal DAC. The reference output is available at the

VREF pin and must be bypassed to the AGND pin with a

0.1µF ceramic capacitor in parallel with a 22µF or greater

electrolytic capacitor. The electrolytic capacitor’s equiva-

lent series resistance (ESR) must be 100mΩ or less to

properly compensate the reference output buffer. Sanyo’s

organic semiconductor capacitors work well; telephone

and FAX numbers are provided below.

Sanyo Video Components (USA)

Phone: (619) 661-6835

FAX: (619) 661-1055

Sanyo Electric Company, LTD. (Japan)

Phone: 0720-70-1005

FAX: 0720-70-1174

Sanyo Fisher Vertriebs GmbH (Germany)

Phone: 06102-27041, ext. 44

FAX: 06102-27045

www.maximintegrated.com

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