MAX121C データシートの表示（PDF） - Maxim Integrated

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MAX121C

308ksps ADC with DSP Interface and 78dB SINAD

Maxim Integrated 

MAX121

308ksps ADC with DSP Interface and 78dB SINAD

Proper bypassing minimizes reference noise and main-

tains a low impedance at high frequencies. The internal­

reference output buffer can sink up to 5mA from an

external load.

An external reference voltage can be used to overdrive

the MAX121’s internal reference, if the external reference

lies within the range from -5.05V to -5.10V. The external

reference must be capable of sinking a minimum of 5mA.

The external VREF bypass capacitors are still required.

External Clock

The MAX121 requires a TTL-/CMOS-compatible clock

for proper operation. The MAX121 accepts clocks in the

frequency range from 0.1MHz to 5.5MHz when operating

in mode 1 or mode 2 (see the Operating Modes section).

To satisfy the 400ns acquisition-time requirement with 2

clock cycles, the maximum clock frequency is limited to

5MHz when operating in mode 3 (continuous-conversion

mode). The minimum clock frequency in all modes is lim-

ited to 0.1MHz due to the droop rate of the internal T/H.

Output Data Format

The conversion result is output as a 16-bit serial data

stream, starting with the 14 data bits (MSB first) followed

by 2 trailing zeros. The format of the output data is two’s-

complement binary. Data is clocked out of the SDATA pin

on the rising edge of CLKIN.

The output data can be framed using either the FSTRT or

the SFRM output. FSTRT (normally low) goes high for 1

CS

tDA

SDATA, SCLK,

SFRM + FSTRT HIGH

IMPEDEANCE

tDH

OUTPUTS ENABLED

HIGH

IMPEDEANCE

Figure 3. Data-Access + Data-Hold Timing

+5V

SERIAL

OUTPUTS

3kΩ

CL

3kΩ

SERIAL

OUTPUTS

CL

DGND

DGND

a. HIGH-Z TO VOH (tDA)

b. HIGH-Z TO VOL (tDA)

Figure 4. Load Circuits for Data-Access Time

clock cycle preceding the MSB. A falling edge on FSTRT

indicates that the MSB is available on the SDATA output.

The SFRM output (normally high when INVFRM = VDD)

goes low coincident with the MSB appearing at the

SDATA pin. SFRM returns high 16 clock cycles later. The

polarity of SFRM can be inverted by tying the INVFRM

input to DGND. A minimum of 18 clock cycles per conver-

sion is required to obtain a valid SFRM output.

See Figure 3 for the data-access and data-hold timing

diagram if several devices share the serial bus. The

equivalent load circuits for data-access and data-hold tim-

ing are shown in Figures 4 and 5.

Digital Interface

The MAX121 serial interface is compatible with SPI and

QSPI serial interfaces. In addition, two framing signals

(FSTRT and SFRM) are provided to allow the MAX121

to easily interface to most digital-signal processors (DSP)

with no external glue logic. The INVCLK input inverts the

phase of SCLK relative to CLKIN, and the INVFRM input

inverts the phase of the SFRM output. These control

signals allow the MAX121 to directly interface to devices

with many different serial-interface standards. Specific

information for interfacing the MAX121 with SPI, QSPI,

and several DSP devices is included in the Applications

Information section.

+5V

SERIAL

OUTPUTS

3kΩ

10pF

SERIAL

OUTPUTS

3kΩ

10pF

DGND

DGND

a. VOH TO HIGH-Z (tDH)

b. VOL TO HIGH-Z (tDH)

Figure 5. Load Circuits for Data-Hold Time

CS

Q

ENABLE

DIGITAL

OUTPUTS

START

CONVERSION

CONVST

Q

ADC

BUSY

Figure 6. Conversion Control Logic

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