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CS5102A(1995) データシートの表示(PDF) - Cirrus Logic

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CS5102A
(Rev.:1995)
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS5102A Datasheet PDF : 40 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CS5102A
SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)
Parameter
CLKIN Period
CLKIN Low Time
CLKIN High Time
Crystal Frequency
SLEEP Rising to Oscillator Stable
RST Pulse Width
RST to STBY Falling
RST Rising to STBY Rising
CH1/2 Edge to TRK1, TRK2 Rising
CH1/2 Edge to TRK1, TRK2 Falling
HOLD to SSH Falling
HOLD to TRK1, TRK2, Falling
HOLD to TRK1, TRK2, SSH Rising
HOLD Pulse Width
HOLD to CH1/2 Edge
HOLD Falling to CLKIN Falling
Symbol Min
Typ
Max Units
(Note 18,24) tclk
0.5
-
10
µs
tclkl
200
-
-
ns
tclkh
200
-
-
ns
(Note 24, 25) fxtal
0.9
1.6
2.0 MHz
(Note 26) -
-
20
-
ms
(Note 27)
(Note 27)
(Note 28)
(Note 28)
(Note 28)
(Note 29)
(Note 28)
(Note 29)
trst
tdrrs
tcal
tdrsh1
tdfsh4
tdfsh2
tdfsh1
tdrsh
thold
tdhlri
thcf
150
-
-
ns
-
100
-
ns
- 2,882,040 -
tclk
-
80
-
ns
-
- 68tclk+260 ns
-
60
ns
66tclk
- 68tclk+260 ns
-
120
-
ns
1tclk+20
-
63tclk
ns
15
-
64tclk
ns
55
-
1tclk+10 ns
Note:
24. Minimum CLKIN period is 0.625 µs in FRN mode (20 kHz sample rate). At temperatures >+85 °C,
and with clock frequencies <1.6 MHz, analog performance may be degraded.
25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency
is 1.6 MHz in FRN mode (20 kHz sample rate).
26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 Mparallel resistor (see Figure 8).
27. These times are for FRN mode.
28. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge
occurs after HOLD rises to 64 tclk after HOLD has fallen. These times are for PDT and RBT modes.
29. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must
be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN
after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as
narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after HOLD falls. This
ensures that the HOLD pulse will meet the minimum specification for thcf.
DS45F2
7

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