CS61581(2005) データシートの表示（PDF） - Cirrus Logic

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CS61581
(Rev.:2005)

T1/E1 Universal Line Interface

Cirrus Logic 

CS61581

2.4.1 Receiver

The receiver extracts data and clock from the input

signal and outputs clock and synchronized data.

The RTIP and RRING inputs are biased to an inter-

mediate DC level so that the input is received as a

differential signal. The incoming pulses are ampli-

fied, equalized and filtered before being fed to the

comparator for peak detection, slicing and data re-

covery. A noise and cross-talk filter removes signal

components that are coupled onto the line from oth-

er cables. T1 or E1 operation is determined by the

transmit pulse shape selection, LEN[2:0].

The clock and data recovery circuit exceeds the jit-

ter tolerance specifications of Publications 43802,

43801, AT&T 62411, TR-TSY-000170, ITU-T

G.823 and ETSI TBR12/13. Jitter tolerance is

shown in Figure 8.

In Hardware mode, the receiver is configured for

Long Haul operation. In Host mode Short Haul op-

eration can be selected by setting the SH/LH

(CR2.0) to 1. When configured for short haul, the

functions of registers 0x10 and 0x11 are redefined.

2.4.2 Short Haul

Receiver sensitivity is set to comply with ITU-T

I.431 requirements for E1 and T1. The comparator

thresholds are dynamically established at 50% per-

cent of the peak level. This is acceptable for both

T1 and E1 cases as pulse undershoot and overshoot

are filtered internally.

2.4.3 Long Haul

Configuring the receiver for long haul operation in-

creases the receive sensitivity. To select long haul

mode, the SH/LH (CR2.0) bit must be set to 0; for

E1 long haul mode, the E1_LH bit (CR3.6) must be

set to 1.

2.4.4 Clock Recovery

The clock recovery circuit is a third-order phase

lock loop. The clock and data recovery circuit is

tolerant of long strings of consecutive zeros, and

will successfully receive a 1-in-175, jitter-free in-

put signal.

In Hardware mode, data on RPOS and RNEG

(RDATA), is stable on the rising edge of recovered

clock, RCLK. In host mode, CLKE (pin 28) deter-

mines the clock polarity for which output data is

valid, as shown in Table 2. When CLKE is high,

RPOS and RNEG (RDATA) are valid on the fall-

ing edge of RCLK. When CLKE is low, RPOS and

RNEG are valid on the rising edge of RCLK.

300

138

100

28

10

PEAK-TO-PEAK

JITTER

(unit intervals)

1

.4

.1

1

Minimum

Performance

AT&T 62411

G. 823

10

100 300 700 1k

10k

JITTER FREQUENCY

(Hz)

100k

Figure 8. Minimum Input Jitter Tolerance of Receiver

MODE

(pin 5)

CLKE

(pin 28)

DATA

CLOCK

Clock Edge for

Valid Data

LOW

HIGH

HIGH

Don’t RPOS RCLK

Care RNEG

LOW

RPOS

RNEG

SDO

RCLK

RCLK

SCLK

HIGH RPOS RCLK

RNEG RCLK

SDO SCLK

Rising

Rising

Rising

Falling

Falling

Falling

Rising

Table 2. Data Output/Clock Relationship

DS211PF1P8

13

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