CS61581(2005) データシートの表示（PDF） - Cirrus Logic
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CS61581 Datasheet PDF : 37 Pages
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CS61581
0
10
20
30
40 Maximum
Attenuation
50 Limit
60
1
10
Minimum Attenuation Limit
62411 Requirements
Measured Performance
100
1k
10 k
Frequency in Hz
Figure 10. Typical Jitter Transfer Function - T1
0
G.736
10
TBR12/13
20
Minimum Attenuation Limits
30
40
50
60
Measured Performance
1
20
2400
18 k
100 k
Frequency in Hz
Figure 11. Typical Jitter Transfer Function - E1
ited using the ANSI T1.231-1993 and ITU-T G.775
criteria, namely 12.5% ones density for 175+/-75
bit periods with no more than 100 consecutive ze-
ros.
In Long Haul operation, the receiver recovers signals
down to -40 dB for T1 and -36 dB for E1. In Short
Haul mode, the receive sensitivity is typically -
21 dB for T1 and -15 dB for E1, in accordance with
I.431 and G.775. LOS will be declared beyond
these signal levels. These LOS thresholds are com-
pliant with all Short Haul applications.
In LOS, the RCLK frequency depends on whether
MCLK is applied, and whether the jitter attenuator
is in the transmit or receive path. If the jitter atten-
uator is in the receive path, the jitter attenuator will
hold over the average incoming data frequency pri-
or to LOS. RPOS (RDATA) and RNEG pins are
forced low upon LOS.
When the jitter attenuator is in the transmit path or
not used, the clock recovery is referenced to
MCLK, if provided, or the crystal oscillator. The
frequency of RCLK in this case will simply remain
slaved to the clock reference upon loss of data. The
recovered clock remains as a 50% duty cycle clock.
The digital PLL in the clock recovery circuit of the
CS61581 generates an internal data clock from the
edges of the incoming pulses (1’s).
Timing is recovered by a phase selector which se-
lects one of the phases from the internal synchroni-
zation clock (one of three clocks, 120 degrees apart
in phase, at 16X the data rate). Since the selection
is made between a limited set of phases, the Digital
Timing Recovery process has a small phase error
built into the sampling process. By choosing 48
possible sampling phases, the CS61581 reduces the
sampling error to a minimum.
2.8 Local Loopback
Local loopback is selected by setting LLOOP high
(pin 27 in Hardware mode, CR1.6 in Host mode).
Selecting local loopback causes the clock and data
on TCLK, TPOS and TNEG (TDATA) to be output
on RCLK, RPOS and RNEG (RDATA). The
RTIP/RRING inputs have no effect on RCLK,
RPOS and RNEG (RDATA) in this mode. Inputs to
the transmitter are still transmitted on TTIP and
TRING unless TAOS has been selected, in which
case AMI-encoded continuous ones are transmitted
at the TCLK frequency.
DS211PF1P8
15
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