CS61582 データシートの表示（PDF） - Cirrus Logic

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CS61582

Dual T1/E1 Line Interface

Cirrus Logic 

Capture-IR State

In this controller state, the shift register con-

tained in the instruction register loads a fixed

value of "01" on the rising edge of J-TCK. This

supports fault-isolation of the board-level serial

test data path.

Data registers selected by the current instruction

retain their value during this state. The instruc-

tions does not change in this state.

When the controller is in this state and a rising

edge is applied to J-TCK, the controller enters

the Exit1-IR state if J-TMS is held high, or the

Shift-IR state if J-TMS is held low.

Shift-IR State

In this state, the shift register contained in the

instruction register is connected between J-TDI

and J-TDO and shifts data one stage towards its

serial output on each rising edge of J-TCK.

The test data register selected by the current in-

struction retains its previous value during this

state. The instruction does not change in this

state.

When the controller is in this state and a rising

edge is applied to J-TCK, the controller enters

the Exit1-IR state if J-TMS is held high, or re-

mains in the Shift-IR state if J-TMS is held low.

Exit1-IR State

This is a temporary state. While in this state, if

J-TMS is held high, a rising edge applied to J-

TCK causes the controller to enter the Update-IR

state, which terminates the scanning process. If

J-TMS is held low and a rising edge is applied

to J-TCK, the controller enters the Pause-IR

state.

The test data register selected by the current in-

struction retains its previous value during this state.

The instruction does not change in this state.

Pause-IR State

The pause state allows the test controller to tem-

porarily halt the shifting of data through the

instruction register.

The test data register selected by the current in-

struction retains its previous value during this

state. The instruction does not change in this

state.

The controller remains in this state as long as

J-TMS is low. When J-TMS goes high and a

rising edge is applied to J-TCK, the controller

moves to the Exit2-IR state.

Exit2-IR State

This is a temporary state. While in this state, if

J-TMS is held high, a rising edge applied to J-

TCK causes the controller to enter the Update-IR

state, which terminates the scanning process. If

J-TMS is held low and a rising edge is applied

to J-TCK, the controller enters the Shift-IR state.

The test data register selected by the current in-

struction retains its previous value during this

state. The instruction does not change in this

state.

Update-IR State

The instruction shifted into the instruction regis-

ter is latched into the parallel output from the

shift-register path on the falling edge of J-TCK.

When the new instruction has been latched, it

becomes the current instruction.

Test data registers selected by the current in-

struction retain their previous value.

JTAG Application Examples

Figures 12 and 13 illustrate examples of updat-

ing the instruction and data registers during

JTAG operation.

18

DS224PP1

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