CS7666 データシートの表示（PDF） - Cirrus Logic

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CS7666

Digital Color-Space Processor for CCD Cameras

Cirrus Logic 

CS7666

ible with one of the analog encoders that can be

used with a given imager. If an analog encoder is

used in the camera to generate an analog output, the

pixel clock frequency expected by the encoder

must be matched precisely. However, digital dis-

play systems, such as those based on VGA graphics

adapter cards and Zoom Video systems, are gener-

ally not sensitive to pixel clock frequency, and will

tolerate a wide range of pixel and frame rates.

Specific pixel-rate clock frequencies for analog en-

coders include 14.31818 MHz for 768H imagers,

the primary ITU-601 13.5 MHz for 720H imagers,

and down to 12.272727 MHz clock rates for 640H

VGA format imagers.

In CS7665 compatibility mode (register 04h bit 4 =

0), The CLKIN2X, pin 56, will either require a

2.5X CCD pixel rate clock when the internal 4:5

scaler is enabled (INTERP pin high) or a 2x times

the CCD pixel rate clock in non-interpolation

mode (INTERP pin low). The CLKIN2X pin is

used as a crystal input pin when the CS7666 is in

native mode (register 04h bit4 = 1).

CLKOUT

CLKOUT follows the output data rate as described

in the Digital Output Formats section. In the non-

interleaved mode the clock output is at the output

luma sample rate whereas in the interleaved mode

the clock output is at 2x the output luma sample

rate.

INTERNAL PROCESSING

The internal operation of the CS7666 can be sepa-

rated into several distinct blocks. The following

section provides an overview of how these blocks

operate and interact.

Input Data Format and Chroma Separator

The CS7666 accepts up to 10-bit MYCG image

data from a CCD digitizer such as the CS7615.

suitable CCD analog processing unit. The CS7666

internally converts the four-color CCD MYCG in-

terlaced image data into the various color space for-

mats. These include RGB and YUV, as well as

YCrCb. The individual image adjustments are per-

formed in the most appropriate color space repre-

sentation. Ultimately the image is converted to

YCrCb format for outputting data.

Color Saturation Control

Color saturation control is via the Red Saturation

and the Blue Saturation control register addresses

0Ah and 0Bh.

White Balance and Gamma Correction

The red and blue color balances can be adjusted

through the I2C control port. During the AWB (au-

tomatic white balance) sequence the red level is ad-

justed to minimize the (Y-R) difference

component; similarly the blue level is adjusted to

minimize the (Y-B) color difference component.

An automatic white balance is initiated by writing

a 1 to register 05h bit 1. For manual control, the red

balance is accessed through register 08h, and the

blue balance is accessed through register 09h.

Gamma correction is provided to offset the non-lin-

ear illumination profile of the display device. Sep-

arate 256 entry tables are supplied for red, green,

and blue. Each entry is 8-bits. The gamma table is

programmed through register 0Ch. The write for-

mat is similar to the write format described in the

normal I2C operation section later in this docu-

ment. The first byte contains the CS7666 device

address and write bit, the second byte contains the

CS7666 gamma table register address (0Ch), the

third byte determines which gamma RAM to up-

date (red, green, and blue), the next 256 bytes con-

tain the gamma table entries.

The blue gamma RAM is selected by setting regis-

ter 0Ch bit 0 to a one; the green gamma RAM is se-

lected by setting register 0Ch bit 1 to a one; and the

red gamma RAM is selected by setting register 0Ch

bit2 to a one. Any, or all of the gamma RAMs may

be selected . The most common implementation is

DS302PP1

15

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