CS7666 データシートの表示（PDF） - Cirrus Logic

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CS7666

Digital Color-Space Processor for CCD Cameras

Cirrus Logic 

CS7666

to write the same gamma table to all 3 RAMs by

setting bits 0-2 high. The gamma table itself is

loaded from low to high. The first byte after the

RAM selection byte will correspond to the value

used when the input data is 00h, the 256th byte after

the RAM selection byte will correspond to the val-

ue used when the input data is FFh.

The gamma table is read in a similar manner. How-

ever, certain restrictions are made to reads. First,

the gamma RAMs may only be read one at a time

(RAM selection byte = 01,02,04 only) and, second,

the gamma table may only be read when gamma

correction is disabled (register 05 bit2 = 0).

Chroma Kill

As the brightness of an image increases, the green,

yellow, cyan, and magenta pixels within the CCD

array will saturate at different intensity levels. As a

result, a highly illuminated object or light source

may start to look cyan. To overcome this effect, an

internal Chroma killer circuit compares the luma

and chroma values of each pixel to a set of pro-

grammable thresholds. If the pixel’s luma value is

greater than the Y_THR value (register 27h) and its

Cr and Cb values are between the CR_THR_H ,

CR_THR_L , CB_THR_H, and CB_THR_L

threshold values respectively, then that pixel will

lose its chroma value (become white.) These

thresholds are stored in registers 27h - 2Ch.

Internal Filters

The CS7666 has an internal low-pass chroma filter

to reduce the effects of color aliasing. This filter is

enabled by writing a value of 0 to bit 4 of register

05h. The CS7666 also contains a luma peaking fil-

ter to enhance the edges of blurred images. This fil-

ter is enabled by setting register 05h bit 3 to a value

of 0.

INTERNAL REGISTER STRUCTURE

AND USER INTERFACE

The user interface describes the user’s external

view of the CS7666 and the basic control opera-

tions. These areas include digital data output modes

and organization, timing and synchronization sig-

nals, I2C interface, and miscellaneous controls.

The CS7666 has two I2C ports: (1) a slave I2C port

called the primary I2C port, and (2) a secondary I2C

port with limited I2C master capabilities. The pri-

mary I2C port allows an external controller to con-

trol the CS7666. It is assumed the external

controller will also directly control any other I2C

slave devices on the camera board. This is the nor-

mal I2C operation mode of CS7666. The secondary

I2C port, on the other hand, may be used to control

all the other slave devices on a camera board

through the CS7666 only. This feature is useful

when the external I2C controller is used to control

multiple cameras. When used in this configuration

the 4BYTEMODE pin (pin 1) of the CS7666 must

be tied high and the device is operated in four-byte

mode.

Operating CS7666 in Normal I2C

Configuration (Three-Byte Mode)

In normal mode, the CS7666 is connected as a

slave device to an external I2C controller through

the primary I2C port. The connection is done via a

two-wire serial bus. Other I2C devices on the cam-

era may also share the same serial bus. The external

controller communicates with the I2C devices by

sending and receiving short packets of 8-bit words

in accordance with the I2C protocol. The packets

contain the station address of the target device, the

desired register address, and data.

There are three packet formats: WRITE format,

ADDRESS SET format, and READ format. Each

packet is addressed to a device by the station ad-

dress. The LSB of the station address is the R/W

(data direction) bit. This bit is set LOW in the

WRITE and ADDRESS SET packets, and it is set

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DS302PP1

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