CY14B101L-SP25XCT データシートの表示（PDF） - Cypress Semiconductor
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CY14B101L-SP25XCT Datasheet PDF : 18 Pages
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PRELIMINARY
CY14B101L
Preventing AutoStore
Disable the AutoStore function by initiating an AutoStore
Disable sequence. A sequence of READ operations is
performed in a manner similar to the software STORE initi-
ation. To initiate the AutoStore Disable sequence, the following
sequence of CE-controlled READ operations must be
performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following sequence of
CE-controlled READ operations must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore
enabled.
Data Protection
The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC < VSWITCH. If the CY14B101L is in a WRITE mode
(CE and WE low) at power up after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative transition
on CE or WE is detected.
This protects against inadvertent writes during power up or
brownout conditions.
Noise Considerations
The CY14B101L is a high speed memory and so must have a
high frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals reduces circuit
noise.
Low Average Active Power
CMOS technology provides the CY14B101L the benefit of
drawing less current when it is cycled at times longer than
50ns. Figure 2 shows the relationship between ICC and
READ/WRITE cycle time. Worst case current consumption is
shown for commercial temperature range VCC = 3.6V and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn
by the CY14B101L depends on the following items:
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. IO loading.
Figure 2. Current vs. Cycle Time
Document #: 001-06400 Rev. *E
Page 6 of 18
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