CY14B101LA データシートの表示（PDF） - Cypress Semiconductor

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CY14B101LA

1 Mbit (128K x 8/64K x 16) nvSRAM

Cypress Semiconductor 

PRELIMINARY

CY14B101LA, CY14B101NA

Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 14, 18]

Address

CE

OE

BHE, BLE

Data Output

High Impedance

ICC

Standby

Address Valid

tRC

tACE

tAA

tLZCE

tLZOE

tDOE

tDBE

tLZBE

tPU

Active

tHZCE

tHZOE

tHZBE

Output Data Valid

tPD

Address

CE

BHE, BLE

WE

Data Input

Data Output

Figure 8. SRAM Write Cycle #1: WE Controlled [3, 17, 18, 21]

tWC

Address Valid

tSCE

tHA

tSA

Previous Data

tBW

tAW

tPWE

tHZWE

tSD

tHD

Input Data Valid

tLZWE

High Impedance

Note

21. CE or WE must be > VIH during address transitions.

Document #: 001-42879 Rev. *C

Page 11 of 24

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