UPD703003 データシートの表示（PDF） - NEC => Renesas Technology

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UPD703003

V853™ 32/16-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD703003

7. CLOCK GENERATION FUNCTIONS

The features of the clock generation functions are shown below.

• Multiplier function using PLL clock synthesizer

• Clock sources

• Oscillation via resonator connection (PLL mode): fXX = φ, 2 × φ, φ/5

• External clock (PLL mode): fXX = φ, 2 × φ, φ/5

• External clock (direct mode): fXX = 2 × φ

• Power saving control

• HALT mode

• IDLE mode

• Software STOP mode

• Clock output inhibit mode

The configuration of the clock generation functions is shown below.

Figure 7-1. Block Diagram of Clock Generation Functions

X1

(fXX)

X2

φ

CPU, On-chip peripheral I/O

Clock generator

CLKOUT

CKSEL

Remark φ : internal system clock

Data Sheet U12261EJ2V1DS00

21

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