UPD703003 データシートの表示（PDF） - NEC => Renesas Technology

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UPD703003

V853™ 32/16-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD703003

The configuration of the asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below.

Figure 9-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)

RXDn

TXDn

Internal bus

16/8

Receive RXBn

buffer RXBnL 8

8

ASIMn0

16/8

TXEn RXEn PSn1 PSn0 CLn SLn SCLSn

8

ASIMn1

EBSn

Receive

shift register

ASISn

PEn FEn OVEn SOTn

Transmit TXSn

shift register TXSnL

Reception

control

parity check

INTSRn

Transmission

INTSERn control parity

attachment

INTSTn

1

1

16

16

φ

1

2

Baud rate generator

Remark n = 0, 1

φ : internal system clock

Data Sheet U12261EJ2V1DS00

25

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