CF52005-3.0 データシートの表示（PDF） - Altera Corporation

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CF52005-3.0

Configuration Devices for SRAM-Based LUT Devices

Altera Corporation 

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

Page 15

Figure 4 shows the timing requirements for the JTAG signals.

Figure 4. EPC2 Device JTAG Waveforms

TMS

TDI

TCK

TDO

Signal

to be

Captured

Signal

to be

Driven

tJCH

tJCP

tJCL

tJPSU

tJPZX

tJSSU

tJSZX

tJPCO

tJSH

tJSCO

tJPH

tJPXZ

tJSXZ

Table 7 lists the timing parameters and values for configuration devices.

Table 7. JTAG Timing Parameters and Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK clock period

100

—

ns

tJCH

TCK clock high time

50

—

ns

tJCL

TCK clock low time

50

—

ns

tJPSU

JTAG port setup time

20

—

ns

tJPH

JTAG port hold time

45

—

ns

tJPCO

JTAG port clock to output

—

25

ns

tJPZX

JTAG port high impedance to valid output

—

25

ns

tJPXZ

JTAG port valid output to high impedance

—

25

ns

tJSSU

Capture register setup time

20

—

ns

tJSH

Capture register hold time

45

—

ns

tJSCO

Update register clock to output

—

25

ns

tJSZX

Update register high impedance to valid output

—

25

ns

tJSXZ

Update register valid output to high impedance

—

25

ns

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

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