CF52005-3.0 データシートの表示（PDF） - Altera Corporation
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CF52005-3.0 Datasheet PDF : 26 Pages
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Page 16
Timing Information
Timing Information
Figure 5 shows the timing waveform when using a configuration device.
Figure 5. Timing Waveform Using a Configuration Device
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA
tOEZX
User I/O
INIT_DONE
tDSU tCL
D0 D1
tCO
Tri-State
tCH
tDH
D2 D3
Dn
Tri-State
(1)
User Mode
Note to Figure 5:
(1) The EPC2 device drives DCLK low and DATA high after configuration. The EPC1 and EPC1441 devices drive DCLK low and tri-state DATA after
configuration.
Table 8 lists the timing parameters when using EPC2 devices at 3.3 V.
Table 8. Timing Parameters when Using EPC2 devices at 3.3 V
Symbol
Parameter
Min
Typ
Max Units
tPO R
POR delay (1)
—
—
200
ms
tOEZX
OE high to DATA output enabled
—
—
80
ns
tCE
OE high to first rising edge on DCLK
—
—
300
ns
tDSU
Data setup time before rising edge on DCLK
30
—
—
ns
tDH
Data hold time after rising edge on DCLK
0
—
—
ns
tCO
DCLK to DATA out
—
—
30
ns
tCD OE
DCLK to DATA enable/disable
—
—
30
ns
fCLK
DCLK frequency
5
7.7
12.5 MHz
tMCH
DCLK high time for the first device in the configuration chain
40
65
100
ns
tMCL
DCLK low time for the first device in the configuration chain
40
65
100
ns
tSCH
DCLK high time for subsequent devices
40
—
—
ns
tSCL
DCLK low time for subsequent devices
40
—
—
ns
tCASC
DCLK rising edge to nCASC
—
—
25
ns
tCCA
nCS to nCASC cascade delay
—
—
15
ns
tOEW
OE low pulse width (reset) to guarantee counter reset
100
—
—
ns
tOEC
OE low (reset) to DCLK disable delay
—
—
30
ns
tNRCAS
OE low (reset) to nCASC delay
—
—
30
ns
Note to Table 8:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation
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