HT46R14A データシートの表示（PDF） - Holtek Semiconductor
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HT46R14A Datasheet PDF : 49 Pages
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HT46R14A
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme allows each instruction
to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are in-
T1 T2 T3 T4 T1
S y s te m C lo c k
cremented by 1. The program counter then points to the
memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manages the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T2 T3 T4 T1 T2 T3 T4
O S C 2 ( R C o n ly )
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Initial Reset
External Interrupt 0
External Interrupt 1
Comparator 0 interrupt
Comparator 1 interrupt
External Interrupt 2
Multi-function Interrupt
Skip
Loading PCL
Jump, Call Branch
*11 *10 *9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*11 *10 *9
#11 #10 #9
Program Counter
*8 *7 *6 *5 *4 *3 *2 *1 *0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
Program Counter+2
*8 @7 @6 @5 @4 @3 @2 @1 @0
#8 #7 #6 #5 #4 #3 #2 #1 #0
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
Program Counter
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.00
6
August 3, 2007
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