HT46R32 データシートの表示（PDF） - Holtek Semiconductor

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HT46R32

A/D Type 8-Bit OTP MCU with OPA

Holtek Semiconductor 

HT46R32/HT46R34

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked by clearing the EMI bit. This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt requires servicing within the service routine, the

EMI bit and the corresponding bit in INTC may be set to

allow interrupt nesting. If the stack is full, the interrupt re-

quest will not be acknowledged, even if the related inter-

rupt is enabled, until the stack pointer is decremented. If

immediate service is desired, the stack must be pre-

vented from becoming full.

All interrupts have a wake-up capability. As an interrupt

is serviced, a control transfer occurs by pushing the pro-

gram counter onto the stack, followed by a branch to a

subroutine at a specified location in the program mem-

ory. Only the program counter is pushed onto the stack.

If the contents of the register or status register are al-

tered by the interrupt service program which corrupts

the desired control sequence, the contents should be

saved in advance.

External interrupts are triggered by a high to low transi-

tion on the INT pin, which will set the related interrupt re-

quest flag, EIF, which is bit 4 of INTC. When the interrupt

is enabled, the stack is not full and the external interrupt

is active, a subroutine call to location 04H will occur. The

interrupt request flag, EIF, and EMI bits will be cleared to

disable other interrupts.

The internal timer/event counter interrupt is initialised by

setting the timer/event counter interrupt request flag, TF,

which is bit 5 of INTC, caused by a timer overflow. When

the interrupt is enabled, the stack is not full and the TF

bit is set, a subroutine call to location 08H will occur. The

related interrupt request flag, TF, will be reset and the

EMI bit cleared to disable further interrupts.

The A/D converter interrupt is initialised by setting the

A/D converter request flag, ADF, which is bit 6 of INTC,

caused by an end of A/D conversion. When the interrupt

is enabled, the stack is not full and the ADF bit is set, a

subroutine call to location 0CH will occur. The related in-

terrupt request flag, ADF, will be reset and the EMI bit

cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1. Of course, the stack

must not be full. To return from the interrupt subroutine,

a RET or RETI instruction may be executed. A RETI in-

struction will set the EMI bit to enable an interrupt ser-

vice, but a RET instruction will not.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority

External Interrupt

1

Timer/Event Counter Overflow

2

A/D Converter Interrupt

3

Vector

004H

008H

00CH

Once the interrupt request flags, TF, EIF, ADF, are set,

they will remain in the INTC register until the interrupts

are serviced or cleared by a software instruction.

It is recommended that a program does not use the CALL

subroutine within the interrupt subroutine. Interrupts of-

ten occur in an unpredictable manner or need to be ser-

viced immediately in some applications. If only one stack

is left and enabling the interrupt is not well controlled, the

original control sequence will be damaged once the

²CALL² operates in the interrupt subroutine.

Oscillator Configuration

There are two oscillator circuits in the microcontroller,

namely an RC oscillator and a crystal oscillator, the

choice of which is determined by a configuration option.

When the system enters the Power-down mode the sys-

tem oscillator stops and ignores external signals to con-

serve power.

If an RC oscillator is used, an external resistor between

OSC1 and VSS is required whose resistance value

must range from 24kW to 1MW. The system clock, di-

vided by 4, can be monitored on pin OSC2 if a pull-high

resistor is connected. This signal can be used to syn-

chronise external logic. The RC oscillator provides the

most cost effective solution, however the frequency of

oscillation may vary with VDD, temperature and the

process variations. It is, therefore, not suitable for tim-

ing sensitive operations where an accurate oscillator

frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator; no other external compo-

nents are required. Instead of a crystal, a resonator can

also be connected between OSC1 and OSC2 to get a

frequency reference, but two external capacitors in

OSC1 and OSC2 are required, If the oscillating fre-

quency is less than 1MHz.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and requires no external components. Even if the

system enters the power down mode, the system clock

O SC1

V DD

470pF

O SC1

O SC2

fS Y S /4

O SC2

C r y s ta l O s c illa to r

R C O s c illa to r

System Oscillator

Rev. 1.10

10

March 16, 2007

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