HYS72D128300GBR-5-B データシートの表示（PDF） - Infineon Technologies

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HYS72D128300GBR-5-B

184-Pin Registered Double Data Rate SDRAM Module

Infineon Technologies 

HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B

Registered Double Data Rate SDRAM Module

Electrical Characteristics

Table 8 IDD Conditions

Parameter

Operating Current 0

one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

Operating Current 1

one bank; active/read/precharge; Burst Length = 4; see component data sheet.

Precharge Power-Down Standby Current

all banks idle; power-down mode; CKE ≤ VIL,MAX

Precharge Floating Standby Current

CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;

address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.

Precharge Quiet Standby Current

CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;

address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.

Active Power-Down Standby Current

one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.

Active Standby Current

one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;

DQ, DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle.

Operating Current Read

one bank active; Burst Length = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA

Operating Current Write

one bank active; Burst Length = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B

Auto-Refresh Current

tRC = tRFCMIN, burst refresh

Self-Refresh Current

CKE ≤ 0.2 V; external clock on

Operating Current 7

four bank interleaving with Burst Length = 4; see component data sheet.

Symbol

IDD0

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

IDD6

IDD7

Data Sheet

16

Rev. 0.5, 2003-12

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