IDT49C460 データシートの表示（PDF） - Integrated Device Technology

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IDT49C460

32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

Integrated Device Technology 

IDT49C460/A/B/C/D/E

32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING MODE SELECTION

Tables 2 and 3 describe the nine operating modes of the

IDT49C460s. The Diagnostic Mode pins — DIAG MODE0,1

— define four basic areas of operation. GENERATE and

CORRECT further divide operation into 8 functions, with

CODE ID1,0 defining the ninth mode as the Internal Mode.

Generate Mode is used to display the check bits on the

outputs SC0–7. The Diagnostic Generate Mode displays

check bits as stored in the Diagnostic Latch.

Detect Mode provides an indication of errors or multiple

errors on the outputs ERROR and MULT ERROR. Single bit

errors are not corrected in this mode. The syndrome bits are

provided on the outputs SC0–7. For the Diagnostic Detect

Mode, the syndrome bits are generated by comparing the

internally generated check bits from the Data In Latch with

check bits stored in the diagnostic latch rather than with the

check bit latch contents.

Correct Mode is similar to the Detect Mode except that

single bit errors will be complemented (corrected) and made

available as input to the Data Out Latches. Again, the

Diagnostic Correct Mode will correct single bit errors as

determined by syndrome bits generated from the data input

and contents of the diagnostic latches.

The Initialize Mode provides check bits for all zero bit data.

Data Input Latches are set, latched to a logic zero and made

available as input to the Data Out Latches.

The Internal Mode disables the external control pins DIAG

MODE0,1 and CORRECT to be defined by the Diagnostic

Latch. Even CODE ID1,0, although externally set to the 01

code, can be redefined from the Diagnostic Latch data.

Code ID1

0

0

1

1

Code ID0

Slice Selected

0

32-Bit

1

Internal Control Mode

0

64-Bit, Lower 32–Bit (0–31)

1

64-Bit, Upper 32-Bit (32–63)

2584 tbl 04

Table 4. Slice Identification

DATA0–31 HIGH C6 C5 C4 C3 C2 C1 C0

CHECK–BIT INPUTS

DATA INPUT

DATA32–63 DATA0–31

32

8

DATA

CB0–7 OESC

IDT49C460

32 (LOWER 32 BITS)

CODE ID1,0

SC0–7

OESC

1/8

IDT74FCT240

1,0

DATA0–31 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0

8

IDT49C460

CODE ID1,0

0,0

SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0

NC

S5/C5

S3/C3

S1/C1

S6/C6

S4/C4

S2/C2

S0/C0

Figure 1. 32-Bit Configuration

2584 drw 05

DATA CB0–7

OESC

IDT49C460

(UPPER 32 BITS)

MULT CODE ID1,0

ERROR ERROR SC0–7

8

MERURLOTR

ERROR

SYNDROME/

CHECK BITS

1,1

2584 drw 06

Figure 2. 64-Bit Configuration

DATA

CHECK BITS

BYTE3 BYTE2 BYTE1 BYTE0 C0 C1 C2 C3 C4

31 24 23 16 15 8 7

0

Figure 3. 32-Bit Data Format

C5 C6

2584 drw 07

DATA

CHECK BITS

BYTE7 BYTE6 BYTE5 BYTE4 BYTE3 BYTE2 BYTE1 BYTE0 C0 C1 C2 C3 C4 C5 C6 C7

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7

0

Figure 4. 64-Bit Data Format

2584 drw 08

11.6

8

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