ISL3685 データシートの表示（PDF） - Intersil
部品番号
コンポーネント説明
メーカー
ISL3685 Datasheet PDF : 19 Pages
| |||
ISL3685
Reference Frequency Counter/Divider
BIT
DESCRIPTION
R(0-14)
Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down
by this counter and is compared with a divided LO by a phase detector.
LO Frequency Counters/Dividers
BIT
DESCRIPTION
A(0-6)
B(0-11)
Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11-bit divider.
The LO frequency is divided down by [P*B+A], where P is the Prescaler divider set by bit M(2). This divided signal frequency is
compared by a phase detector with the divided Reference signal.
Operational Modes
BIT
DESCRIPTION
M(0)
(PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on.
M(2)
Prescaler Select. 0 = 32/33, 1 = 64/65.
M(3)
M(4)
Charge Pump Current Setting
M(4)
0
M(3)
0
OUTPUT SINK/SOURCE
0.25mA
0
1
0.50mA
1
0
0.75mA
1
1
1.00mA
M(5)
M(6)
Charge Pump Sign
M(7)
M(8)
M(13)
LD Pin Multiplex Operation
M(6)
0
0
M(13)
0
0
M(5)
0
1
M(8)
0
1
Source if LO/ [P*B+A] < Ref/R
Source if LO/ [P*B+A] > Ref/R
M(7)
OUTPUT AT PIN LD
X
Lock Detect Operation
X
Short to GND
1
0
X
Serial Register Read Back
1
1
0
Ref. Divided by R Waveform
1
1
1
LO Divided by [P*B+A]
Waveform
M(14)
M(15)
Charge Pump Operation/Test
M(15)
0
M(14)
0
OPERATION/TEST
Normal Operation
0
1
Charge Pump Constant Current Source
1
0
Charge Pump Constant Current Sink
1
1
High Impedance State
7
Share Link: 