LC573102A データシートの表示（PDF） - SANYO -> Panasonic

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LC573102A

4-bit Single Chip Microcontroller

SANYO -> Panasonic 

LC573104A, 573102A

Continued from preceding page.

Mnemonic Instruction code

Function

SDPL

0 0 0 1 1 1 0 0 DPL ← (AC)

SDPH

0 0 0 1 1 1 0 1 DPH ← (AC)

LDPL

1 1 1 1 1 1 0 1 AC ← (DPL)

LDPH

1 1 1 1 1 1 1 0 AC ← (DPH)

MDPL X 1 0 1 1 X3X2X1X0 DPL ← X

MDPH X 1 1 0 0 X3X2X1X0 DPH ← X

EDPL

0 0 0 1 1 1 1 0 (DPL) ↔ (EDPL)

EDPH

0 0 0 1 1 1 1 1 (DPH) ↔ (EDPH)

IDPL

1 0 0 1 1 0 1 0 DPL ← (DPL)+1

IDPH

1 0 0 1 1 1 0 0 DPH ← (DPH)+1

DDPL

1 0 0 1 1 0 1 1 DPL ← (DPL)–1

DDPH

1 0 0 1 1 1 0 1 DPH ← (DPH)–1

SSP

1 0 1 0 1 1 1 0 SP ← (AC)

LSP

1 0 1 0 1 0 1 0 AC ← (SP)

MSP X

ISP

1 1 1 0 X3X2X1X0 SP ← X

1 0 0 1 1 1 1 0 SP ← (SP)+1

DSP

1 0 0 1 1 1 1 1 SP ← (SP)–1

LHLT

1 0 1 0 1 0 1 1 AC ← (STS2), STS2 ← 0

L500

1 0 1 0 1 1 0 0 AC ← (STS1), SCF0 ← 0

CSP

0 0 0 0 0 1 0 0 CSTF ← 0

CST

0 0 0 0 0 1 0 1 CSTF ← 1

RC5

0 0 0 0 0 1 1 0 HEF0 ← 0

SC5

0 0 0 0 0 1 1 1 HEF0 ← 1

RCF

1 1 1 1 0 0 0 0 CF ← 0

SCF

1 1 1 1 0 0 0 1 CF ← 1

LDA

1 0 1 0 1 0 0 1 AC ← [M (DP)]

STA

1 0 1 0 1 1 0 1 M (DP) ← (AC)

LDI X

MVI X

0 0 1 1 X3X2X1X0 AC ← X

0 0 1 0 X3X2X1X0 M (DP) ← X

Function description

1 1 AC contents loaded to DPL.

Status

flag

affected

1 1 AC contents loaded to DPH.

1 1 DPL contents loaded to AC.

1 1 DPH contents loaded to AC.

1 1 Immediate data X loaded to DPL.

1 1 Immediate data X loaded to DPH.

1 1 DPL and EDPL contents exchanged.

1 1 DPH and EDPH contents exchanged.

1 1 DPL contents incremented +1.

1 1 DPH contents incremented +1.

1 1 DPL contents decremented –1.

1 1 DPH contents decremented –1.

1 1 AC contents loaded to SP.

1 1 SP contents loaded to AC.

1 1 Immediate data X loaded to SP.

1 1 SP contents incremented +1.

1 1 SP contents decremented –1.

1 1 STS2 contents loaded to AC and STS2 is reset.

1 1 STS1 contents loaded to AC and SCF0 is reset.

SCF1 to

SCF4

SCF0

1 1 CSTF reset.

CSTF

1 1 CSTF set.

CSTF

1 1 HEF0 reset to inhibit Halt mode release by overflow from the divider circuit. HEF0

1 1 HEF0 set enabling overflow from the divider circuit to release the Halt mode. HEF0

1 1 CF reset.

CF

1 1 CF set.

CF

1 1 Memory M (DP) contents transferred to AC.

1 1 AC contents stored in memory M (DP).

1 1 Immediate data X loaded to AC.

1 1 Immediate data X loaded to memory M (DP).

Continued on next page.

No.4144–13/16

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