LC573102A データシートの表示（PDF） - SANYO -> Panasonic

部品番号

コンポーネント説明

メーカー

LC573102A

4-bit Single Chip Microcontroller

SANYO -> Panasonic 

LC573104A, 573102A

Continued from preceding page.

Mnemonic Instruction code

Function

JMP X

BAB0 X

BAB1 X

BAB2 X

BAB3 X

BAZ X

BANZ X

BCNH X

BCH X

PAGE

0 0 0 0 1 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 0 0 1 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 0 1 1 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 1 0 1 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 1 1 1 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 0 0 0 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 0 1 0 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 1 0 0 X10X9X8

X7X6X5X4 X3X2X1X0

0 1 1 1 0 X10X9X8

X7X6X5X4 X3X2X1X0

0001 0001

(PC10 to PC0) ← X10 to X0

If AC0=1 then

(PC10 to PC0) ← X10 to X0

If AC1=1 then

(PC10 to PC0) ← X10 to X0

If AC2=1 then

(PC10 to PC0) ← X10 to X0

If AC3=1 then

(PC10 to PC0) ← X10 to X0

If AC=0 then

(PC10 to PC0) ← X10 to X0

If AC≠0 then

(PC10 to PC0) ← X10 to X0

If CF≠1 then

(PC10 to PC0) ← X10 to X0

If CF=1 then

(PC10 to PC0) ← X10 to X0

PAGE ← [M (DP)]

JMP*

ROM0

ROM1

JSR X

RST

0001

1100

0010

0000

1000

0000

PC10 to PC08 ← (PAGE)

PC07 to PC04 ← (AC)

PC03 to PC00 ← [M (DP)]

PC11 ← 0

1100

0010

1 0 0 0 PC11 ← 1

0001

1 0 1 0 0 X10X9X8

X7X6X5X4 X3X2X1X0

0001 0011

STACK ← (PC)+2

(PC10 to PC0) ← X10 to X0

PC ← (STACK)

SPC0

SPC1

CSEC

1100

0010

1100

0010

1111

1001

0000

1001

0001

1011

SPC ← 0

SPC ← 1

φ11 to φ15 ← 0

RWDT

1 1 1 1 1 0 0 1 (WDT) ← 0

Function description

2 2 Loads data specified by X10 to X0 to PC and jumps unconditionally.

Status

flag

affected

2 2 When AC bit 0 is '1', data specified by X10 to X0 is loaded to PC and jumps.

At '0', PC is incremented +2.

2 2 When AC bit 1 is '1', data specified by X10 to X0 is loaded to PC and jumps.

At '0', PC is incremented +2.

2 2 When AC bit 2 is '1', data specified by X10 to X0 is loaded to PC and jumps.

At '0', PC is incremented +2.

2 2 When AC bit 3 is '1', data specified by X10 to X0 is loaded to PC and jumps.

At '0', PC is incremented +2.

2 2 When AC is '0', data specified by X10 to X0 is loaded to PC and jumps.

When AC is not '0', PC is incremented +2.

2 2 When AC is not '0', data specified by X10 to X0 is loaded to PC and jumps.

When AC is '0', PC is incremented +2.

2 2 When CF is '0', data specified by X10 to X0 is loaded to PC and jumps.

When CF is '1', PC is incremented +2.

2 2 When CF is '1', data specified by X10 to X0 is loaded to PC and jumps.

When CF is '0', PC is incremented +2.

1 1 Memory M (DP) contents loaded to PAGE latch.

1 1 Unconditionally jumps to page specified by PAGE and address whose low-

order 8 bits are specified by contents of AC and memory M (DP).

2 2 Select ROM bank 0.

2 2 Select ROM bank 1.

2 2 Current PC+2 contents are saved in STACK, data specified by X10 to X0 is

loaded to PC and sub-routine is called.

1 1 Returns PC contents saved in STACK to PC and returns from sub-routine.

2 2 Resets strobe pointer control bit (SPC) to '0'.

SPC

2 2 Sets strobe pointer control bit (SPC) to '1'.

SPC

1 1 Resets high-order 4 bits of divider circuit.

1 1 Resets Watchdog Timer counter.

SCF0

SCF4

No.4144–15/16

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