LFECP10E-5T144I データシートの表示（PDF） - Lattice Semiconductor

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LFECP10E-5T144I

LatticeECP/EC Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeECP/EC Family Data Sheet

Routing

There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with

related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)

segments.

The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).

The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and

x6 resources are buffered, the routing of both short and long connections between PFUs.

The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally,

the place and route tool is completely automatic, although an interactive routing editor is available to optimize the

design.

Clock Distribution Network

The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed

through the chip via a clock distribution system.

Primary Clock Sources

LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.

LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There

are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.

Figure 2-6. Primary Clock Sources

From Routing

Clock Input

From Routing

PLL Input

PLL

PLL

PLL Input

Clock Input

20 Primary Clock Sources

To Quadrant Clock Selection

Clock Input

PLL Input

PLL

PLL

PLL Input

From Routing

Clock Input

Note: Smaller devices have two PLLs.

From Routing

2-7

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