LFECP10E-5F484C データシートの表示（PDF） - Lattice Semiconductor
部品番号
コンポーネント説明
メーカー
LFECP10E-5F484C Datasheet PDF : 163 Pages
| |||
Lattice Semiconductor
Architecture
LatticeECP/EC Family Data Sheet
Table 2-7. Maximum Number of Elements in a Block
Width of Multiply
x9
MULT
8
MAC
2
MULTADD
4
MULTADDSUM
2
x18
x36
4
1
2
—
2
—
1
—
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the
‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly
by selecting ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and
subtraction on every cycle.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-19 shows the MULT sysDSP element.
Figure 2-19. MULT sysDSP Element
Shift Register B In
Shift Register A In
Multiplicand
m
m
Multiplier
Signed
n
n
n
Input Data
Register B
n
m
Input Data
m
Register A
n
m
Multiplier
x
m+n
(default)
Pipeline
Register
m+n
Output
Input
Register
To
Multiplier
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered overflow
signal is also available. The overflow conditions are provided later in this document. Figure 2-20 shows the MAC
sysDSP element.
2-16
Share Link: 